\doxysection{stm32\+\_\+hal\+\_\+legacy.\+h}
\hypertarget{stm32__hal__legacy_8h_source}{}\label{stm32__hal__legacy_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/Legacy/stm32\_hal\_legacy.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/Legacy/stm32\_hal\_legacy.h}}
\mbox{\hyperlink{stm32__hal__legacy_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00030\ \textcolor{comment}{/*\ Exported\ constants\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
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\DoxyCodeLine{01607\ \textcolor{preprocessor}{\#define\ ETH\_MAC\_TRANSMISSION\_PAUSE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 0x00080000U\ \ }\textcolor{comment}{/*\ MAC\ transmitter\ in\ pause\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01611\ \textcolor{preprocessor}{\#define\ ETH\_MAC\_TRANSMITFRAMECONTROLLER\_GENRATING\_PCF\ 0x00040000U\ \ }\textcolor{comment}{/*\ MAC\ transmit\ frame\ controller:\ Generating\ and\ }}
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\DoxyCodeLine{01615\ \textcolor{preprocessor}{\#define\ ETH\_MAC\_MII\_TRANSMIT\_ACTIVE\ \ \ \ \ \ \ \ \ \ \ 0x00010000U\ \ }\textcolor{comment}{/*\ MAC\ MII\ transmit\ engine\ active\ */}\textcolor{preprocessor}{}}
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\DoxyCodeLine{01866\ \textcolor{preprocessor}{\#define\ HAL\_I2C\_Master\_Sequential\_Receive\_DMA\ \ HAL\_I2C\_Master\_Seq\_Receive\_DMA}}
\DoxyCodeLine{01867\ \textcolor{preprocessor}{\#define\ HAL\_I2C\_Slave\_Sequential\_Transmit\_DMA\ \ HAL\_I2C\_Slave\_Seq\_Transmit\_DMA}}
\DoxyCodeLine{01868\ \textcolor{preprocessor}{\#define\ HAL\_I2C\_Slave\_Sequential\_Receive\_DMA\ \ \ HAL\_I2C\_Slave\_Seq\_Receive\_DMA}}
\DoxyCodeLine{01869\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7\ ||\ STM32WB\ \ ||\ STM32G0\ ||\ STM32F4\ ||\ STM32F7\ ||\ STM32L0\ ||\ STM32L4\ ||\ STM32L5\ ||\ STM32G4\ ||\ STM32L1\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{01870\ }
\DoxyCodeLine{01871\ \textcolor{preprocessor}{\#if\ defined(STM32F4)}}
\DoxyCodeLine{01872\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Master\_Sequential\_Transmit\_IT\ \ HAL\_FMPI2C\_Master\_Seq\_Transmit\_IT}}
\DoxyCodeLine{01873\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Master\_Sequential\_Receive\_IT\ \ \ HAL\_FMPI2C\_Master\_Seq\_Receive\_IT}}
\DoxyCodeLine{01874\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Slave\_Sequential\_Transmit\_IT\ \ \ HAL\_FMPI2C\_Slave\_Seq\_Transmit\_IT}}
\DoxyCodeLine{01875\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Slave\_Sequential\_Receive\_IT\ \ \ \ HAL\_FMPI2C\_Slave\_Seq\_Receive\_IT}}
\DoxyCodeLine{01876\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Master\_Sequential\_Transmit\_DMA\ HAL\_FMPI2C\_Master\_Seq\_Transmit\_DMA}}
\DoxyCodeLine{01877\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Master\_Sequential\_Receive\_DMA\ \ HAL\_FMPI2C\_Master\_Seq\_Receive\_DMA}}
\DoxyCodeLine{01878\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Slave\_Sequential\_Transmit\_DMA\ \ HAL\_FMPI2C\_Slave\_Seq\_Transmit\_DMA}}
\DoxyCodeLine{01879\ \textcolor{preprocessor}{\#define\ HAL\_FMPI2C\_Slave\_Sequential\_Receive\_DMA\ \ \ HAL\_FMPI2C\_Slave\_Seq\_Receive\_DMA}}
\DoxyCodeLine{01880\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32F4\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{01884\ }
\DoxyCodeLine{01888\ }
\DoxyCodeLine{01889\ \textcolor{preprocessor}{\#if\ defined(STM32G0)}}
\DoxyCodeLine{01890\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_ConfigPVD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_ConfigPVD}}
\DoxyCodeLine{01891\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_EnablePVD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnablePVD}}
\DoxyCodeLine{01892\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_DisablePVD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisablePVD}}
\DoxyCodeLine{01893\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_PVD\_IRQHandler\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_PVD\_IRQHandler}}
\DoxyCodeLine{01894\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{01895\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_PVDConfig\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWR\_ConfigPVD}}
\DoxyCodeLine{01896\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_DisableBkUpReg\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableBkUpReg}}
\DoxyCodeLine{01897\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_DisableFlashPowerDown\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableFlashPowerDown}}
\DoxyCodeLine{01898\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_DisableVddio2Monitor\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableVddio2Monitor}}
\DoxyCodeLine{01899\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_EnableBkUpReg\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableBkUpReg}}
\DoxyCodeLine{01900\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_EnableFlashPowerDown\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableFlashPowerDown}}
\DoxyCodeLine{01901\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_EnableVddio2Monitor\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableVddio2Monitor}}
\DoxyCodeLine{01902\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_PVD\_PVM\_IRQHandler\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_PVD\_PVM\_IRQHandler}}
\DoxyCodeLine{01903\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_PVDLevelConfig\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWR\_ConfigPVD}}
\DoxyCodeLine{01904\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_Vddio2Monitor\_IRQHandler\ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_Vddio2Monitor\_IRQHandler}}
\DoxyCodeLine{01905\ \textcolor{preprocessor}{\#define\ HAL\_PWR\_Vddio2MonitorCallback\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_Vddio2MonitorCallback}}
\DoxyCodeLine{01906\ \textcolor{preprocessor}{\#define\ HAL\_PWREx\_ActivateOverDrive\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableOverDrive}}
\DoxyCodeLine{01907\ \textcolor{preprocessor}{\#define\ HAL\_PWREx\_DeactivateOverDrive\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableOverDrive}}
\DoxyCodeLine{01908\ \textcolor{preprocessor}{\#define\ HAL\_PWREx\_DisableSDADCAnalog\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableSDADC}}
\DoxyCodeLine{01909\ \textcolor{preprocessor}{\#define\ HAL\_PWREx\_EnableSDADCAnalog\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableSDADC}}
\DoxyCodeLine{01910\ \textcolor{preprocessor}{\#define\ HAL\_PWREx\_PVMConfig\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_ConfigPVM}}
\DoxyCodeLine{01911\ }
\DoxyCodeLine{01912\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_NORMAL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_NORMAL}}
\DoxyCodeLine{01913\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_IT\_RISING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_IT\_RISING}}
\DoxyCodeLine{01914\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_IT\_FALLING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_IT\_FALLING}}
\DoxyCodeLine{01915\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_IT\_RISING\_FALLING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_IT\_RISING\_FALLING}}
\DoxyCodeLine{01916\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_EVENT\_RISING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_EVENT\_RISING}}
\DoxyCodeLine{01917\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_EVENT\_FALLING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_EVENT\_FALLING}}
\DoxyCodeLine{01918\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_EVENT\_RISING\_FALLING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_EVENT\_RISING\_FALLING}}
\DoxyCodeLine{01919\ }
\DoxyCodeLine{01920\ \textcolor{preprocessor}{\#define\ CR\_OFFSET\_BB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_CR\_OFFSET\_BB}}
\DoxyCodeLine{01921\ \textcolor{preprocessor}{\#define\ CSR\_OFFSET\_BB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_CSR\_OFFSET\_BB}}
\DoxyCodeLine{01922\ \textcolor{preprocessor}{\#define\ PMODE\_BIT\_NUMBER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ VOS\_BIT\_NUMBER}}
\DoxyCodeLine{01923\ \textcolor{preprocessor}{\#define\ CR\_PMODE\_BB\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CR\_VOS\_BB}}
\DoxyCodeLine{01924\ }
\DoxyCodeLine{01925\ \textcolor{preprocessor}{\#define\ DBP\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ DBP\_BIT\_NUMBER}}
\DoxyCodeLine{01926\ \textcolor{preprocessor}{\#define\ PVDE\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PVDE\_BIT\_NUMBER}}
\DoxyCodeLine{01927\ \textcolor{preprocessor}{\#define\ PMODE\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PMODE\_BIT\_NUMBER}}
\DoxyCodeLine{01928\ \textcolor{preprocessor}{\#define\ EWUP\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ EWUP\_BIT\_NUMBER}}
\DoxyCodeLine{01929\ \textcolor{preprocessor}{\#define\ FPDS\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ FPDS\_BIT\_NUMBER}}
\DoxyCodeLine{01930\ \textcolor{preprocessor}{\#define\ ODEN\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ODEN\_BIT\_NUMBER}}
\DoxyCodeLine{01931\ \textcolor{preprocessor}{\#define\ ODSWEN\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ODSWEN\_BIT\_NUMBER}}
\DoxyCodeLine{01932\ \textcolor{preprocessor}{\#define\ MRLVDS\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ MRLVDS\_BIT\_NUMBER}}
\DoxyCodeLine{01933\ \textcolor{preprocessor}{\#define\ LPLVDS\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ LPLVDS\_BIT\_NUMBER}}
\DoxyCodeLine{01934\ \textcolor{preprocessor}{\#define\ BRE\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ BRE\_BIT\_NUMBER}}
\DoxyCodeLine{01935\ }
\DoxyCodeLine{01936\ \textcolor{preprocessor}{\#define\ PWR\_MODE\_EVT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PVD\_MODE\_NORMAL}}
\DoxyCodeLine{01937\ }
\DoxyCodeLine{01938\ \textcolor{preprocessor}{\#if\ defined\ (STM32U5)}}
\DoxyCodeLine{01939\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE1\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE1\_STOP}}
\DoxyCodeLine{01940\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE2\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE2\_STOP}}
\DoxyCodeLine{01941\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE3\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE3\_STOP}}
\DoxyCodeLine{01942\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE4\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE4\_STOP}}
\DoxyCodeLine{01943\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE5\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE5\_STOP}}
\DoxyCodeLine{01944\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE6\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE6\_STOP}}
\DoxyCodeLine{01945\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE7\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE7\_STOP}}
\DoxyCodeLine{01946\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE8\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE8\_STOP}}
\DoxyCodeLine{01947\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE9\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE9\_STOP}}
\DoxyCodeLine{01948\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE10\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE10\_STOP}}
\DoxyCodeLine{01949\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE11\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE11\_STOP}}
\DoxyCodeLine{01950\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_PAGE12\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_PAGE12\_STOP}}
\DoxyCodeLine{01951\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_FULL\_STOP}}
\DoxyCodeLine{01952\ }
\DoxyCodeLine{01953\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_PAGE1\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_PAGE1\_STOP}}
\DoxyCodeLine{01954\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_PAGE2\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_PAGE2\_STOP}}
\DoxyCodeLine{01955\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_FULL\_STOP}}
\DoxyCodeLine{01956\ }
\DoxyCodeLine{01957\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE1\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE1\_STOP}}
\DoxyCodeLine{01958\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE2\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE2\_STOP}}
\DoxyCodeLine{01959\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE3\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE3\_STOP}}
\DoxyCodeLine{01960\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE4\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE4\_STOP}}
\DoxyCodeLine{01961\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE5\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE5\_STOP}}
\DoxyCodeLine{01962\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE6\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE6\_STOP}}
\DoxyCodeLine{01963\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE7\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE7\_STOP}}
\DoxyCodeLine{01964\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE8\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE8\_STOP}}
\DoxyCodeLine{01965\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE9\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE9\_STOP}}
\DoxyCodeLine{01966\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE10\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE10\_STOP}}
\DoxyCodeLine{01967\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE11\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE11\_STOP}}
\DoxyCodeLine{01968\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE12\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE12\_STOP}}
\DoxyCodeLine{01969\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_PAGE13\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_PAGE13\_STOP}}
\DoxyCodeLine{01970\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_FULL\_STOP}}
\DoxyCodeLine{01971\ }
\DoxyCodeLine{01972\ \textcolor{preprocessor}{\#define\ PWR\_SRAM4\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM4\_FULL\_STOP}}
\DoxyCodeLine{01973\ }
\DoxyCodeLine{01974\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE1\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE1\_STOP}}
\DoxyCodeLine{01975\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE2\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE2\_STOP}}
\DoxyCodeLine{01976\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE3\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE3\_STOP}}
\DoxyCodeLine{01977\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE4\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE4\_STOP}}
\DoxyCodeLine{01978\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE5\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE5\_STOP}}
\DoxyCodeLine{01979\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE6\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE6\_STOP}}
\DoxyCodeLine{01980\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE7\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE7\_STOP}}
\DoxyCodeLine{01981\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE8\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE8\_STOP}}
\DoxyCodeLine{01982\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE9\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE9\_STOP}}
\DoxyCodeLine{01983\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE10\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE10\_STOP}}
\DoxyCodeLine{01984\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE11\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE11\_STOP}}
\DoxyCodeLine{01985\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE12\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE12\_STOP}}
\DoxyCodeLine{01986\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_PAGE13\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_PAGE13\_STOP}}
\DoxyCodeLine{01987\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_FULL\_STOP}}
\DoxyCodeLine{01988\ }
\DoxyCodeLine{01989\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE1\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE1\_STOP}}
\DoxyCodeLine{01990\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE2\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE2\_STOP}}
\DoxyCodeLine{01991\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE3\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE3\_STOP}}
\DoxyCodeLine{01992\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE4\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE4\_STOP}}
\DoxyCodeLine{01993\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE5\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE5\_STOP}}
\DoxyCodeLine{01994\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE6\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE6\_STOP}}
\DoxyCodeLine{01995\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE7\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE7\_STOP}}
\DoxyCodeLine{01996\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_PAGE8\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_PAGE8\_STOP}}
\DoxyCodeLine{01997\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_FULL\_STOP}}
\DoxyCodeLine{01998\ }
\DoxyCodeLine{01999\ }
\DoxyCodeLine{02000\ \textcolor{preprocessor}{\#define\ PWR\_ICACHE\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_ICACHE\_FULL\_STOP}}
\DoxyCodeLine{02001\ \textcolor{preprocessor}{\#define\ PWR\_DCACHE1\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_DCACHE1\_FULL\_STOP}}
\DoxyCodeLine{02002\ \textcolor{preprocessor}{\#define\ PWR\_DCACHE2\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_DCACHE2\_FULL\_STOP}}
\DoxyCodeLine{02003\ \textcolor{preprocessor}{\#define\ PWR\_DMA2DRAM\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_DMA2DRAM\_FULL\_STOP}}
\DoxyCodeLine{02004\ \textcolor{preprocessor}{\#define\ PWR\_PERIPHRAM\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PERIPHRAM\_FULL\_STOP}}
\DoxyCodeLine{02005\ \textcolor{preprocessor}{\#define\ PWR\_PKA32RAM\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_PKA32RAM\_FULL\_STOP}}
\DoxyCodeLine{02006\ \textcolor{preprocessor}{\#define\ PWR\_GRAPHICPRAM\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ PWR\_GRAPHICPRAM\_FULL\_STOP}}
\DoxyCodeLine{02007\ \textcolor{preprocessor}{\#define\ PWR\_DSIRAM\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_DSIRAM\_FULL\_STOP}}
\DoxyCodeLine{02008\ \textcolor{preprocessor}{\#define\ PWR\_JPEGRAM\_FULL\_STOP\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_JPEGRAM\_FULL\_STOP}}
\DoxyCodeLine{02009\ }
\DoxyCodeLine{02010\ }
\DoxyCodeLine{02011\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_PAGE1\_STANDBY\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_PAGE1\_STANDBY}}
\DoxyCodeLine{02012\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_PAGE2\_STANDBY\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_PAGE2\_STANDBY}}
\DoxyCodeLine{02013\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_FULL\_STANDBY\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_FULL\_STANDBY}}
\DoxyCodeLine{02014\ }
\DoxyCodeLine{02015\ \textcolor{preprocessor}{\#define\ PWR\_SRAM1\_FULL\_RUN\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM1\_FULL\_RUN}}
\DoxyCodeLine{02016\ \textcolor{preprocessor}{\#define\ PWR\_SRAM2\_FULL\_RUN\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM2\_FULL\_RUN}}
\DoxyCodeLine{02017\ \textcolor{preprocessor}{\#define\ PWR\_SRAM3\_FULL\_RUN\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM3\_FULL\_RUN}}
\DoxyCodeLine{02018\ \textcolor{preprocessor}{\#define\ PWR\_SRAM4\_FULL\_RUN\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM4\_FULL\_RUN}}
\DoxyCodeLine{02019\ \textcolor{preprocessor}{\#define\ PWR\_SRAM5\_FULL\_RUN\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM5\_FULL\_RUN}}
\DoxyCodeLine{02020\ \textcolor{preprocessor}{\#define\ PWR\_SRAM6\_FULL\_RUN\_RETENTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_SRAM6\_FULL\_RUN}}
\DoxyCodeLine{02021\ }
\DoxyCodeLine{02022\ \textcolor{preprocessor}{\#define\ PWR\_ALL\_RAM\_RUN\_RETENTION\_MASK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ PWR\_ALL\_RAM\_RUN\_MASK}}
\DoxyCodeLine{02023\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02024\ }
\DoxyCodeLine{02028\ }
\DoxyCodeLine{02032\ \textcolor{preprocessor}{\#if\ defined(STM32H5)\ ||\ defined(STM32WBA)\ ||\ defined(STM32H7RS)\ ||\ defined(STM32N6)}}
\DoxyCodeLine{02033\ \textcolor{preprocessor}{\#define\ HAL\_RTCEx\_SetBoothardwareKey\ \ \ \ \ \ \ \ \ \ \ \ HAL\_RTCEx\_LockBootHardwareKey}}
\DoxyCodeLine{02034\ \textcolor{preprocessor}{\#define\ HAL\_RTCEx\_BKUPBlock\_Enable\ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_RTCEx\_BKUPBlock}}
\DoxyCodeLine{02035\ \textcolor{preprocessor}{\#define\ HAL\_RTCEx\_BKUPBlock\_Disable\ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_RTCEx\_BKUPUnblock}}
\DoxyCodeLine{02036\ \textcolor{preprocessor}{\#define\ HAL\_RTCEx\_Erase\_SecretDev\_Conf\ \ \ \ \ \ \ \ \ \ HAL\_RTCEx\_ConfigEraseDeviceSecrets}}
\DoxyCodeLine{02037\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H5\ ||\ STM32WBA\ ||\ STM32H7RS\ ||\ STM32N6\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02038\ }
\DoxyCodeLine{02042\ }
\DoxyCodeLine{02046\ \textcolor{preprocessor}{\#define\ HAL\_SMBUS\_Slave\_Listen\_IT\ \ \ \ \ \ \ \ \ \ HAL\_SMBUS\_EnableListen\_IT}}
\DoxyCodeLine{02047\ \textcolor{preprocessor}{\#define\ HAL\_SMBUS\_SlaveAddrCallback\ \ \ \ \ \ \ \ HAL\_SMBUS\_AddrCallback}}
\DoxyCodeLine{02048\ \textcolor{preprocessor}{\#define\ HAL\_SMBUS\_SlaveListenCpltCallback\ \ HAL\_SMBUS\_ListenCpltCallback}\textcolor{preprocessor}{}}
\DoxyCodeLine{02052\ }
\DoxyCodeLine{02056\ \textcolor{preprocessor}{\#define\ HAL\_SPI\_FlushRxFifo\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_SPIEx\_FlushRxFifo}\textcolor{preprocessor}{}}
\DoxyCodeLine{02060\ }
\DoxyCodeLine{02064\ \textcolor{preprocessor}{\#define\ HAL\_TIM\_DMADelayPulseCplt\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DMADelayPulseCplt}}
\DoxyCodeLine{02065\ \textcolor{preprocessor}{\#define\ HAL\_TIM\_DMAError\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DMAError}}
\DoxyCodeLine{02066\ \textcolor{preprocessor}{\#define\ HAL\_TIM\_DMACaptureCplt\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIM\_DMACaptureCplt}}
\DoxyCodeLine{02067\ \textcolor{preprocessor}{\#define\ HAL\_TIMEx\_DMACommutationCplt\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ TIMEx\_DMACommutationCplt}}
\DoxyCodeLine{02068\ \textcolor{preprocessor}{\#if\ defined(STM32H7)\ ||\ defined(STM32G0)\ ||\ defined(STM32F0)\ ||\ defined(STM32F1)\ ||\ defined(STM32F2)\ ||\ \(\backslash\)}}
\DoxyCodeLine{02069\ \textcolor{preprocessor}{\ \ \ \ defined(STM32F3)\ ||\ defined(STM32F4)\ ||\ defined(STM32F7)\ ||\ defined(STM32L0)\ ||\ defined(STM32L4)}}
\DoxyCodeLine{02070\ \textcolor{preprocessor}{\#define\ HAL\_TIM\_SlaveConfigSynchronization\ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_TIM\_SlaveConfigSynchro}}
\DoxyCodeLine{02071\ \textcolor{preprocessor}{\#define\ HAL\_TIM\_SlaveConfigSynchronization\_IT\ \ \ \ \ \ \ \ \ \ \ HAL\_TIM\_SlaveConfigSynchro\_IT}}
\DoxyCodeLine{02072\ \textcolor{preprocessor}{\#define\ HAL\_TIMEx\_CommutationCallback\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_TIMEx\_CommutCallback}}
\DoxyCodeLine{02073\ \textcolor{preprocessor}{\#define\ HAL\_TIMEx\_ConfigCommutationEvent\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_TIMEx\_ConfigCommutEvent}}
\DoxyCodeLine{02074\ \textcolor{preprocessor}{\#define\ HAL\_TIMEx\_ConfigCommutationEvent\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_TIMEx\_ConfigCommutEvent\_IT}}
\DoxyCodeLine{02075\ \textcolor{preprocessor}{\#define\ HAL\_TIMEx\_ConfigCommutationEvent\_DMA\ \ \ \ \ \ \ \ \ \ \ \ HAL\_TIMEx\_ConfigCommutEvent\_DMA}}
\DoxyCodeLine{02076\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7\ ||\ STM32G0\ ||\ STM32F0\ ||\ STM32F1\ ||\ STM32F2\ ||\ STM32F3\ ||\ STM32F4\ ||\ STM32F7\ ||\ STM32L0\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02080\ }
\DoxyCodeLine{02084\ \textcolor{preprocessor}{\#define\ HAL\_UART\_WakeupCallback\ HAL\_UARTEx\_WakeupCallback}\textcolor{preprocessor}{}}
\DoxyCodeLine{02088\ }
\DoxyCodeLine{02092\ \textcolor{preprocessor}{\#define\ HAL\_LTDC\_LineEvenCallback\ HAL\_LTDC\_LineEventCallback}}
\DoxyCodeLine{02093\ \textcolor{preprocessor}{\#define\ HAL\_LTDC\_Relaod\ \ \ \ \ \ \ \ \ \ \ HAL\_LTDC\_Reload}}
\DoxyCodeLine{02094\ \textcolor{preprocessor}{\#define\ HAL\_LTDC\_StructInitFromVideoConfig\ \ HAL\_LTDCEx\_StructInitFromVideoConfig}}
\DoxyCodeLine{02095\ \textcolor{preprocessor}{\#define\ HAL\_LTDC\_StructInitFromAdaptedCommandConfig\ \ HAL\_LTDCEx\_StructInitFromAdaptedCommandConfig}\textcolor{preprocessor}{}}
\DoxyCodeLine{02099\ }
\DoxyCodeLine{02100\ }
\DoxyCodeLine{02104\ }
\DoxyCodeLine{02108\ }
\DoxyCodeLine{02109\ \textcolor{comment}{/*\ Exported\ macros\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{02110\ }
\DoxyCodeLine{02114\ \textcolor{preprocessor}{\#define\ AES\_IT\_CC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CRYP\_IT\_CC}}
\DoxyCodeLine{02115\ \textcolor{preprocessor}{\#define\ AES\_IT\_ERR\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CRYP\_IT\_ERR}}
\DoxyCodeLine{02116\ \textcolor{preprocessor}{\#define\ AES\_FLAG\_CCF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CRYP\_FLAG\_CCF}\textcolor{preprocessor}{}}
\DoxyCodeLine{02120\ }
\DoxyCodeLine{02124\ \textcolor{preprocessor}{\#define\ \_\_HAL\_GET\_BOOT\_MODE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_GET\_BOOT\_MODE}}
\DoxyCodeLine{02125\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_FLASH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_FLASH}}
\DoxyCodeLine{02126\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_SYSTEMFLASH\ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_SYSTEMFLASH}}
\DoxyCodeLine{02127\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_SRAM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_SRAM}}
\DoxyCodeLine{02128\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_FMC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_FMC}}
\DoxyCodeLine{02129\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_FMC\_SDRAM\ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_FMC\_SDRAM}}
\DoxyCodeLine{02130\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_FSMC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_FSMC}}
\DoxyCodeLine{02131\ \textcolor{preprocessor}{\#define\ \_\_HAL\_REMAPMEMORY\_QUADSPI\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_REMAPMEMORY\_QUADSPI}}
\DoxyCodeLine{02132\ \textcolor{preprocessor}{\#define\ \_\_HAL\_FMC\_BANK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_FMC\_BANK}}
\DoxyCodeLine{02133\ \textcolor{preprocessor}{\#define\ \_\_HAL\_GET\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_GET\_FLAG}}
\DoxyCodeLine{02134\ \textcolor{preprocessor}{\#define\ \_\_HAL\_CLEAR\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_CLEAR\_FLAG}}
\DoxyCodeLine{02135\ \textcolor{preprocessor}{\#define\ \_\_HAL\_VREFINT\_OUT\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_VREFINT\_OUT\_ENABLE}}
\DoxyCodeLine{02136\ \textcolor{preprocessor}{\#define\ \_\_HAL\_VREFINT\_OUT\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_VREFINT\_OUT\_DISABLE}}
\DoxyCodeLine{02137\ \textcolor{preprocessor}{\#define\ \_\_HAL\_SYSCFG\_SRAM2\_WRP\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_SYSCFG\_SRAM2\_WRP\_0\_31\_ENABLE}}
\DoxyCodeLine{02138\ }
\DoxyCodeLine{02139\ \textcolor{preprocessor}{\#define\ SYSCFG\_FLAG\_VREF\_READY\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SYSCFG\_FLAG\_VREFINT\_READY}}
\DoxyCodeLine{02140\ \textcolor{preprocessor}{\#define\ SYSCFG\_FLAG\_RC48\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ RCC\_FLAG\_HSI48}}
\DoxyCodeLine{02141\ \textcolor{preprocessor}{\#define\ IS\_SYSCFG\_FASTMODEPLUS\_CONFIG\ \ \ \ \ \ \ \ \ IS\_I2C\_FASTMODEPLUS}}
\DoxyCodeLine{02142\ \textcolor{preprocessor}{\#define\ UFB\_MODE\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ UFB\_MODE\_BIT\_NUMBER}}
\DoxyCodeLine{02143\ \textcolor{preprocessor}{\#define\ CMP\_PD\_BitNumber\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ CMP\_PD\_BIT\_NUMBER}}
\DoxyCodeLine{02144\ }
\DoxyCodeLine{02148\ }
\DoxyCodeLine{02149\ }
\DoxyCodeLine{02153\ \textcolor{preprocessor}{\#define\ \_\_ADC\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_ADC\_ENABLE}}
\DoxyCodeLine{02154\ \textcolor{preprocessor}{\#define\ \_\_ADC\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_ADC\_DISABLE}}
\DoxyCodeLine{02155\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_ENABLING\_CONDITIONS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_ENABLING\_CONDITIONS}}
\DoxyCodeLine{02156\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_DISABLING\_CONDITIONS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_DISABLING\_CONDITIONS}}
\DoxyCodeLine{02157\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_ENABLED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_IS\_ENABLE}}
\DoxyCodeLine{02158\ \textcolor{preprocessor}{\#define\ \_\_ADC\_IS\_ENABLED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_IS\_ENABLE}}
\DoxyCodeLine{02159\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_SOFTWARE\_START\_REGULAR\ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_IS\_SOFTWARE\_START\_REGULAR}}
\DoxyCodeLine{02160\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_SOFTWARE\_START\_INJECTED\ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_IS\_SOFTWARE\_START\_INJECTED}}
\DoxyCodeLine{02161\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_CONVERSION\_ONGOING\_REGULAR\_INJECTED\ ADC\_IS\_CONVERSION\_ONGOING\_REGULAR\_INJECTED}}
\DoxyCodeLine{02162\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_CONVERSION\_ONGOING\_REGULAR\ \ \ \ \ \ \ \ \ \ ADC\_IS\_CONVERSION\_ONGOING\_REGULAR}}
\DoxyCodeLine{02163\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_CONVERSION\_ONGOING\_INJECTED\ \ \ \ \ \ \ \ \ ADC\_IS\_CONVERSION\_ONGOING\_INJECTED}}
\DoxyCodeLine{02164\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_IS\_CONVERSION\_ONGOING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_IS\_CONVERSION\_ONGOING}}
\DoxyCodeLine{02165\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CLEAR\_ERRORCODE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CLEAR\_ERRORCODE}}
\DoxyCodeLine{02166\ }
\DoxyCodeLine{02167\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_GET\_RESOLUTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_GET\_RESOLUTION}}
\DoxyCodeLine{02168\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_JSQR\_RK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_JSQR\_RK}}
\DoxyCodeLine{02169\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_AWD1CH\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_AWD1CH\_SHIFT}}
\DoxyCodeLine{02170\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_AWD23CR\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_AWD23CR}}
\DoxyCodeLine{02171\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_INJECT\_AUTO\_CONVERSION\ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_INJECT\_AUTO\_CONVERSION}}
\DoxyCodeLine{02172\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_INJECT\_CONTEXT\_QUEUE\ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_INJECT\_CONTEXT\_QUEUE}}
\DoxyCodeLine{02173\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_INJECT\_DISCCONTINUOUS\ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_INJECT\_DISCCONTINUOUS}}
\DoxyCodeLine{02174\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_REG\_DISCCONTINUOUS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_REG\_DISCCONTINUOUS}}
\DoxyCodeLine{02175\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_DISCONTINUOUS\_NUM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_DISCONTINUOUS\_NUM}}
\DoxyCodeLine{02176\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_AUTOWAIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_AUTOWAIT}}
\DoxyCodeLine{02177\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_CONTINUOUS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_CONTINUOUS}}
\DoxyCodeLine{02178\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_OVERRUN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_OVERRUN}}
\DoxyCodeLine{02179\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_DMACONTREQ\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_DMACONTREQ}}
\DoxyCodeLine{02180\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CFGR\_EXTSEL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CFGR\_EXTSEL\_SET}}
\DoxyCodeLine{02181\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_JSQR\_JEXTSEL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_JSQR\_JEXTSEL\_SET}}
\DoxyCodeLine{02182\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_OFR\_CHANNEL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_OFR\_CHANNEL}}
\DoxyCodeLine{02183\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_DIFSEL\_CHANNEL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_DIFSEL\_CHANNEL}}
\DoxyCodeLine{02184\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CALFACT\_DIFF\_SET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CALFACT\_DIFF\_SET}}
\DoxyCodeLine{02185\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CALFACT\_DIFF\_GET\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CALFACT\_DIFF\_GET}}
\DoxyCodeLine{02186\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_TRX\_HIGHTHRESHOLD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_TRX\_HIGHTHRESHOLD}}
\DoxyCodeLine{02187\ }
\DoxyCodeLine{02188\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_OFFSET\_SHIFT\_RESOLUTION\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_OFFSET\_SHIFT\_RESOLUTION}}
\DoxyCodeLine{02189\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_AWD1THRESHOLD\_SHIFT\_RESOLUTION\ \ \ \ \ \ \ \ \ ADC\_AWD1THRESHOLD\_SHIFT\_RESOLUTION}}
\DoxyCodeLine{02190\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_AWD23THRESHOLD\_SHIFT\_RESOLUTION\ \ \ \ \ \ \ \ ADC\_AWD23THRESHOLD\_SHIFT\_RESOLUTION}}
\DoxyCodeLine{02191\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_COMMON\_REGISTER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_COMMON\_REGISTER}}
\DoxyCodeLine{02192\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_COMMON\_CCR\_MULTI\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_COMMON\_CCR\_MULTI}}
\DoxyCodeLine{02193\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_MULTIMODE\_IS\_ENABLED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_MULTIMODE\_IS\_ENABLE}}
\DoxyCodeLine{02194\ \textcolor{preprocessor}{\#define\ \_\_ADC\_MULTIMODE\_IS\_ENABLED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_MULTIMODE\_IS\_ENABLE}}
\DoxyCodeLine{02195\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_NONMULTIMODE\_OR\_MULTIMODEMASTER\ \ \ \ \ \ \ \ ADC\_NONMULTIMODE\_OR\_MULTIMODEMASTER}}
\DoxyCodeLine{02196\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_COMMON\_ADC\_OTHER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_COMMON\_ADC\_OTHER}}
\DoxyCodeLine{02197\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_MULTI\_SLAVE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_MULTI\_SLAVE}}
\DoxyCodeLine{02198\ }
\DoxyCodeLine{02199\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SQR1\_L\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SQR1\_L\_SHIFT}}
\DoxyCodeLine{02200\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_JSQR\_JL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_JSQR\_JL\_SHIFT}}
\DoxyCodeLine{02201\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_JSQR\_RK\_JL\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_JSQR\_RK\_JL}}
\DoxyCodeLine{02202\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CR1\_DISCONTINUOUS\_NUM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CR1\_DISCONTINUOUS\_NUM}}
\DoxyCodeLine{02203\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CR1\_SCAN\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CR1\_SCAN\_SET}}
\DoxyCodeLine{02204\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CONVCYCLES\_MAX\_RANGE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CONVCYCLES\_MAX\_RANGE}}
\DoxyCodeLine{02205\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CLOCK\_PRESCALER\_RANGE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CLOCK\_PRESCALER\_RANGE}}
\DoxyCodeLine{02206\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_GET\_CLOCK\_PRESCALER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_GET\_CLOCK\_PRESCALER}}
\DoxyCodeLine{02207\ }
\DoxyCodeLine{02208\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SQR1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SQR1}}
\DoxyCodeLine{02209\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SMPR1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SMPR1}}
\DoxyCodeLine{02210\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SMPR2\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SMPR2}}
\DoxyCodeLine{02211\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SQR3\_RK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SQR3\_RK}}
\DoxyCodeLine{02212\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SQR2\_RK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SQR2\_RK}}
\DoxyCodeLine{02213\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_SQR1\_RK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_SQR1\_RK}}
\DoxyCodeLine{02214\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CR2\_CONTINUOUS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CR2\_CONTINUOUS}}
\DoxyCodeLine{02215\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ADC\_CR1\_DISCONTINUOUS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ADC\_CR1\_DISCONTINUOUS}}
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\DoxyCodeLine{02359\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02360\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02361\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP6\_EXTI\_DISABLE\_RISING\_EDGE())}}
\DoxyCodeLine{02362\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02363\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02364\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02365\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP6\_EXTI\_ENABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02366\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02367\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02368\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02369\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP6\_EXTI\_DISABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02370\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_ENABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02371\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02372\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02374\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_DISABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02375\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02376\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02377\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP6\_EXTI\_DISABLE\_IT())}}
\DoxyCodeLine{02378\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02379\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02380\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02382\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_CLEAR\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02383\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02384\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02385\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP6\_EXTI\_CLEAR\_FLAG())}}
\DoxyCodeLine{02386\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02387\ \textcolor{preprocessor}{\#if\ defined(STM32F303xE)\ ||\ defined(STM32F398xx)\ ||\ defined(STM32F303xC)\ ||\ defined(STM32F358xx)}}
\DoxyCodeLine{02388\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_RISING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02390\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02391\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02392\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02393\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02395\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_RISING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02396\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02397\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02398\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02399\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02400\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02402\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02404\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02406\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02407\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02408\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP7\_EXTI\_ENABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02409\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02410\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02411\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02413\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02414\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02416\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_ENABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02418\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02419\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02420\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02421\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02423\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_DISABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02425\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02426\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02427\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02428\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02429\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP7\_EXTI\_DISABLE\_IT())}}
\DoxyCodeLine{02430\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02431\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02432\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02433\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02434\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02435\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02436\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP7\_EXTI\_GET\_FLAG())}}
\DoxyCodeLine{02437\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_CLEAR\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02438\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP2)\ ?\ \_\_HAL\_COMP\_COMP2\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02439\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP3)\ ?\ \_\_HAL\_COMP\_COMP3\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02440\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP4)\ ?\ \_\_HAL\_COMP\_COMP4\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02441\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP5)\ ?\ \_\_HAL\_COMP\_COMP5\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02442\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP6)\ ?\ \_\_HAL\_COMP\_COMP6\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02443\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP7\_EXTI\_CLEAR\_FLAG())}}
\DoxyCodeLine{02444\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02445\ \textcolor{preprocessor}{\#if\ defined(STM32F373xC)\ ||defined(STM32F378xx)}}
\DoxyCodeLine{02446\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_RISING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
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\DoxyCodeLine{02448\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_RISING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02449\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_RISING\_EDGE())}}
\DoxyCodeLine{02450\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02451\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02452\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02453\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02454\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_ENABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02455\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_IT())}}
\DoxyCodeLine{02456\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_DISABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02457\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_IT())}}
\DoxyCodeLine{02458\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02459\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_GET\_FLAG())}}
\DoxyCodeLine{02460\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_CLEAR\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02461\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_CLEAR\_FLAG())}}
\DoxyCodeLine{02462\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02463\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02464\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_RISING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02465\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_RISING\_EDGE())}}
\DoxyCodeLine{02466\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_RISING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_RISING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02467\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_RISING\_EDGE())}}
\DoxyCodeLine{02468\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_ENABLE(\_\_EXTILINE\_\_)\ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02469\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02470\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_FALLING\_IT\_DISABLE(\_\_EXTILINE\_\_)\ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_FALLING\_EDGE()\ :\ \(\backslash\)}}
\DoxyCodeLine{02471\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_FALLING\_EDGE())}}
\DoxyCodeLine{02472\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_ENABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_ENABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02473\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_ENABLE\_IT())}}
\DoxyCodeLine{02474\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_DISABLE\_IT(\_\_EXTILINE\_\_)\ \ \ \ \ \ \ \ \ (((\_\_EXTILINE\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_DISABLE\_IT()\ :\ \(\backslash\)}}
\DoxyCodeLine{02475\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_DISABLE\_IT())}}
\DoxyCodeLine{02476\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_GET\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_GET\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02477\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_GET\_FLAG())}}
\DoxyCodeLine{02478\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_EXTI\_CLEAR\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ \ \ \ \ \ \ \ \ (((\_\_FLAG\_\_)\ \ ==\ COMP\_EXTI\_LINE\_COMP1)\ ?\ \_\_HAL\_COMP\_COMP1\_EXTI\_CLEAR\_FLAG()\ :\ \(\backslash\)}}
\DoxyCodeLine{02479\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_COMP\_COMP2\_EXTI\_CLEAR\_FLAG())}}
\DoxyCodeLine{02480\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02481\ }
\DoxyCodeLine{02482\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_GET\_EXTI\_LINE\ \ COMP\_GET\_EXTI\_LINE}}
\DoxyCodeLine{02483\ }
\DoxyCodeLine{02484\ \textcolor{preprocessor}{\#if\ defined(STM32L0)\ ||\ defined(STM32L4)}}
\DoxyCodeLine{02485\ \textcolor{comment}{/*\ Note:\ On\ these\ STM32\ families,\ the\ only\ argument\ of\ this\ macro\ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02486\ \textcolor{comment}{/*\ \ \ \ \ \ \ is\ COMP\_FLAG\_LOCK.\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02487\ \textcolor{comment}{/*\ \ \ \ \ \ \ This\ macro\ is\ replaced\ by\ \_\_HAL\_COMP\_IS\_LOCKED\ with\ only\ HAL\ handle\ \ */}}
\DoxyCodeLine{02488\ \textcolor{comment}{/*\ \ \ \ \ \ \ argument.\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ */}}
\DoxyCodeLine{02489\ \textcolor{preprocessor}{\#define\ \_\_HAL\_COMP\_GET\_FLAG(\_\_HANDLE\_\_,\ \_\_FLAG\_\_)\ \ (\_\_HAL\_COMP\_IS\_LOCKED(\_\_HANDLE\_\_))}}
\DoxyCodeLine{02490\ \textcolor{preprocessor}{\#endif}\textcolor{preprocessor}{}}
\DoxyCodeLine{02494\ }
\DoxyCodeLine{02495\ \textcolor{preprocessor}{\#if\ defined(STM32L0)\ ||\ defined(STM32L4)}\textcolor{preprocessor}{}}
\DoxyCodeLine{02499\ \textcolor{preprocessor}{\#define\ HAL\_COMP\_Start\_IT\ \ \ \ \ \ \ HAL\_COMP\_Start\ }\textcolor{comment}{/*\ Function\ considered\ as\ legacy\ as\ EXTI\ event\ or\ IT\ configuration\ is\ }}
\DoxyCodeLine{02500\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ done\ into\ HAL\_COMP\_Init()\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02501\ \textcolor{preprocessor}{\#define\ HAL\_COMP\_Stop\_IT\ \ \ \ \ \ \ \ HAL\_COMP\_Stop\ \ }\textcolor{comment}{/*\ Function\ considered\ as\ legacy\ as\ EXTI\ event\ or\ IT\ configuration\ is\ }}
\DoxyCodeLine{02502\ \textcolor{comment}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ done\ into\ HAL\_COMP\_Init()\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02506\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{02507\ }
\DoxyCodeLine{02511\ }
\DoxyCodeLine{02512\ \textcolor{preprocessor}{\#define\ IS\_DAC\_WAVE(WAVE)\ (((WAVE)\ ==\ DAC\_WAVE\_NONE)\ ||\ \(\backslash\)}}
\DoxyCodeLine{02513\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((WAVE)\ ==\ DAC\_WAVE\_NOISE)||\ \(\backslash\)}}
\DoxyCodeLine{02514\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((WAVE)\ ==\ DAC\_WAVE\_TRIANGLE))}}
\DoxyCodeLine{02515\ }
\DoxyCodeLine{02519\ }
\DoxyCodeLine{02523\ }
\DoxyCodeLine{02524\ \textcolor{preprocessor}{\#define\ IS\_WRPAREA\ \ \ \ \ \ \ \ \ \ IS\_OB\_WRPAREA}}
\DoxyCodeLine{02525\ \textcolor{preprocessor}{\#define\ IS\_TYPEPROGRAM\ \ \ \ \ \ IS\_FLASH\_TYPEPROGRAM}}
\DoxyCodeLine{02526\ \textcolor{preprocessor}{\#define\ IS\_TYPEPROGRAMFLASH\ IS\_FLASH\_TYPEPROGRAM}}
\DoxyCodeLine{02527\ \textcolor{preprocessor}{\#define\ IS\_TYPEERASE\ \ \ \ \ \ \ \ IS\_FLASH\_TYPEERASE}}
\DoxyCodeLine{02528\ \textcolor{preprocessor}{\#define\ IS\_NBSECTORS\ \ \ \ \ \ \ \ IS\_FLASH\_NBSECTORS}}
\DoxyCodeLine{02529\ \textcolor{preprocessor}{\#define\ IS\_OB\_WDG\_SOURCE\ \ \ \ IS\_OB\_IWDG\_SOURCE}}
\DoxyCodeLine{02530\ }
\DoxyCodeLine{02534\ }
\DoxyCodeLine{02538\ }
\DoxyCodeLine{02539\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_RESET\_CR2\ \ \ \ \ \ \ \ \ \ \ \ \ I2C\_RESET\_CR2}}
\DoxyCodeLine{02540\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_GENERATE\_START\ \ \ \ \ \ \ \ I2C\_GENERATE\_START}}
\DoxyCodeLine{02541\ \textcolor{preprocessor}{\#if\ defined(STM32F1)}}
\DoxyCodeLine{02542\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_FREQ\_RANGE\ \ \ \ \ \ \ \ \ \ \ \ I2C\_FREQRANGE}}
\DoxyCodeLine{02543\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02544\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_FREQ\_RANGE\ \ \ \ \ \ \ \ \ \ \ \ I2C\_FREQ\_RANGE}}
\DoxyCodeLine{02545\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32F1\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02546\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_RISE\_TIME\ \ \ \ \ \ \ \ \ \ \ \ \ I2C\_RISE\_TIME}}
\DoxyCodeLine{02547\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_SPEED\_STANDARD\ \ \ \ \ \ \ \ I2C\_SPEED\_STANDARD}}
\DoxyCodeLine{02548\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_SPEED\_FAST\ \ \ \ \ \ \ \ \ \ \ \ I2C\_SPEED\_FAST}}
\DoxyCodeLine{02549\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_SPEED\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ I2C\_SPEED}}
\DoxyCodeLine{02550\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_7BIT\_ADD\_WRITE\ \ \ \ \ \ \ \ I2C\_7BIT\_ADD\_WRITE}}
\DoxyCodeLine{02551\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_7BIT\_ADD\_READ\ \ \ \ \ \ \ \ \ I2C\_7BIT\_ADD\_READ}}
\DoxyCodeLine{02552\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_10BIT\_ADDRESS\ \ \ \ \ \ \ \ \ I2C\_10BIT\_ADDRESS}}
\DoxyCodeLine{02553\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_10BIT\_HEADER\_WRITE\ \ \ \ I2C\_10BIT\_HEADER\_WRITE}}
\DoxyCodeLine{02554\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_10BIT\_HEADER\_READ\ \ \ \ \ I2C\_10BIT\_HEADER\_READ}}
\DoxyCodeLine{02555\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_MEM\_ADD\_MSB\ \ \ \ \ \ \ \ \ \ \ I2C\_MEM\_ADD\_MSB}}
\DoxyCodeLine{02556\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_MEM\_ADD\_LSB\ \ \ \ \ \ \ \ \ \ \ I2C\_MEM\_ADD\_LSB}}
\DoxyCodeLine{02557\ \textcolor{preprocessor}{\#define\ \_\_HAL\_I2C\_FREQRANGE\ \ \ \ \ \ \ \ \ \ \ \ \ I2C\_FREQRANGE}\textcolor{preprocessor}{}}
\DoxyCodeLine{02561\ }
\DoxyCodeLine{02565\ }
\DoxyCodeLine{02566\ \textcolor{preprocessor}{\#define\ IS\_I2S\_INSTANCE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ IS\_I2S\_ALL\_INSTANCE}}
\DoxyCodeLine{02567\ \textcolor{preprocessor}{\#define\ IS\_I2S\_INSTANCE\_EXT\ \ \ \ \ \ \ \ \ \ \ \ \ IS\_I2S\_ALL\_INSTANCE\_EXT}}
\DoxyCodeLine{02568\ }
\DoxyCodeLine{02569\ \textcolor{preprocessor}{\#if\ defined(STM32H7)}}
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\DoxyCodeLine{02581\ \textcolor{preprocessor}{\#define\ \_\_IRDA\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_IRDA\_DISABLE}}
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\DoxyCodeLine{02584\ \textcolor{preprocessor}{\#define\ \_\_HAL\_IRDA\_GETCLOCKSOURCE\ \ \ \ \ \ \ IRDA\_GETCLOCKSOURCE}}
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\DoxyCodeLine{02589\ \textcolor{preprocessor}{\#define\ IS\_IRDA\_ONEBIT\_SAMPLE\ \ \ \ \ \ \ \ \ \ \ IS\_IRDA\_ONE\_BIT\_SAMPLE}}
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\DoxyCodeLine{02595\ }
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\DoxyCodeLine{02600\ \textcolor{preprocessor}{\#define\ \_\_HAL\_IWDG\_ENABLE\_WRITE\_ACCESS\ \ IWDG\_ENABLE\_WRITE\_ACCESS}}
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\DoxyCodeLine{02623\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_CSR\_OPAXPD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ OPAMP\_CSR\_OPAXPD}}
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\DoxyCodeLine{02645\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EVENT\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT}}
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\DoxyCodeLine{02648\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_FALLINGTRIGGER\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}}
\DoxyCodeLine{02649\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_RISINGTRIGGER\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE}}
\DoxyCodeLine{02650\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_RISINGTRIGGER\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}}
\DoxyCodeLine{02651\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVM\_EVENT\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVM\_EVENT\_DISABLE}}
\DoxyCodeLine{02652\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVM\_EVENT\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVM\_EVENT\_ENABLE}}
\DoxyCodeLine{02653\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVM\_EXTI\_FALLINGTRIGGER\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVM\_EXTI\_FALLINGTRIGGER\_DISABLE}}
\DoxyCodeLine{02654\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVM\_EXTI\_FALLINGTRIGGER\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVM\_EXTI\_FALLINGTRIGGER\_ENABLE}}
\DoxyCodeLine{02655\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVM\_EXTI\_RISINGTRIGGER\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVM\_EXTI\_RISINGTRIGGER\_DISABLE}}
\DoxyCodeLine{02656\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVM\_EXTI\_RISINGTRIGGER\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVM\_EXTI\_RISINGTRIGGER\_ENABLE}}
\DoxyCodeLine{02657\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_INTERNALWAKEUP\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableInternalWakeUpLine}}
\DoxyCodeLine{02658\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_INTERNALWAKEUP\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableInternalWakeUpLine}}
\DoxyCodeLine{02659\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PULL\_UP\_DOWN\_CONFIG\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisablePullUpPullDownConfig}}
\DoxyCodeLine{02660\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PULL\_UP\_DOWN\_CONFIG\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnablePullUpPullDownConfig}}
\DoxyCodeLine{02661\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_EGDE\_TRIGGER()\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ do\ \{\ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE();\ \(\backslash\)}}
\DoxyCodeLine{02662\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE();\ \(\backslash\)}}
\DoxyCodeLine{02663\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02664\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_EVENT\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_EVENT}}
\DoxyCodeLine{02665\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_EVENT\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_EVENT}}
\DoxyCodeLine{02666\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_FALLINGTRIGGER\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_FALLING\_EDGE}}
\DoxyCodeLine{02667\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_FALLINGTRIGGER\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}}
\DoxyCodeLine{02668\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_RISINGTRIGGER\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_RISING\_EDGE}}
\DoxyCodeLine{02669\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_RISINGTRIGGER\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}}
\DoxyCodeLine{02670\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_SET\_FALLING\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_FALLING\_EDGE}}
\DoxyCodeLine{02671\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVD\_EXTI\_SET\_RISING\_EDGE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_RISING\_EDGE}}
\DoxyCodeLine{02672\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVM\_DISABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ do\ \{\ HAL\_PWREx\_DisablePVM1();HAL\_PWREx\_DisablePVM2();\ \(\backslash\)}}
\DoxyCodeLine{02673\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisablePVM3();HAL\_PWREx\_DisablePVM4();\ \(\backslash\)}}
\DoxyCodeLine{02674\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02675\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_PVM\_ENABLE()\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ do\ \{\ HAL\_PWREx\_EnablePVM1();HAL\_PWREx\_EnablePVM2();\ \(\backslash\)}}
\DoxyCodeLine{02676\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnablePVM3();HAL\_PWREx\_EnablePVM4();\ \(\backslash\)}}
\DoxyCodeLine{02677\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{02678\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_SRAM2CONTENT\_PRESERVE\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableSRAM2ContentRetention}}
\DoxyCodeLine{02679\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_SRAM2CONTENT\_PRESERVE\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableSRAM2ContentRetention}}
\DoxyCodeLine{02680\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VDDIO2\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableVddIO2}}
\DoxyCodeLine{02681\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VDDIO2\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableVddIO2}}
\DoxyCodeLine{02682\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VDDIO2\_EXTI\_CLEAR\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_VDDIO2\_EXTI\_DISABLE\_FALLING\_EDGE}}
\DoxyCodeLine{02683\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VDDIO2\_EXTI\_SET\_FALLING\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_VDDIO2\_EXTI\_ENABLE\_FALLING\_EDGE}}
\DoxyCodeLine{02684\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VDDUSB\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_DisableVddUSB}}
\DoxyCodeLine{02685\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PWR\_VDDUSB\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PWREx\_EnableVddUSB}}
\DoxyCodeLine{02686\ }
\DoxyCodeLine{02687\ \textcolor{preprocessor}{\#if\ defined\ (STM32F4)}}
\DoxyCodeLine{02688\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_ENABLE\_IT(PWR\_EXTI\_LINE\_PVD)\ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT()}}
\DoxyCodeLine{02689\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_DISABLE\_IT(PWR\_EXTI\_LINE\_PVD)\ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT()}}
\DoxyCodeLine{02690\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_GET\_FLAG(PWR\_EXTI\_LINE\_PVD)\ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG()}}
\DoxyCodeLine{02691\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_CLEAR\_FLAG(PWR\_EXTI\_LINE\_PVD)\ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG()}}
\DoxyCodeLine{02692\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_GENERATE\_SWIT(PWR\_EXTI\_LINE\_PVD)\ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT()}}
\DoxyCodeLine{02693\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{02694\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_CLEAR\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_CLEAR\_FLAG}}
\DoxyCodeLine{02695\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_DISABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_DISABLE\_IT}}
\DoxyCodeLine{02696\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_ENABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_ENABLE\_IT}}
\DoxyCodeLine{02697\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_GENERATE\_SWIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_GENERATE\_SWIT}}
\DoxyCodeLine{02698\ \textcolor{preprocessor}{\#define\ \_\_HAL\_PVD\_EXTI\_GET\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_PWR\_PVD\_EXTI\_GET\_FLAG}}
\DoxyCodeLine{02699\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32F4\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{02703\ }
\DoxyCodeLine{02704\ }
\DoxyCodeLine{02708\ }
\DoxyCodeLine{02709\ \textcolor{preprocessor}{\#define\ RCC\_StopWakeUpClock\_MSI\ \ \ \ \ RCC\_STOP\_WAKEUPCLOCK\_MSI}}
\DoxyCodeLine{02710\ \textcolor{preprocessor}{\#define\ RCC\_StopWakeUpClock\_HSI\ \ \ \ \ RCC\_STOP\_WAKEUPCLOCK\_HSI}}
\DoxyCodeLine{02711\ }
\DoxyCodeLine{02712\ \textcolor{preprocessor}{\#define\ HAL\_RCC\_CCSCallback\ HAL\_RCC\_CSSCallback}}
\DoxyCodeLine{02713\ \textcolor{preprocessor}{\#define\ HAL\_RC48\_EnableBuffer\_Cmd(cmd)\ (((cmd)==ENABLE)\ ?\ \(\backslash\)}}
\DoxyCodeLine{02714\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_RCCEx\_EnableHSI48\_VREFINT()\ :\ HAL\_RCCEx\_DisableHSI48\_VREFINT())}}
\DoxyCodeLine{02715\ }
\DoxyCodeLine{02716\ \textcolor{preprocessor}{\#define\ \_\_ADC\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC\_CLK\_DISABLE}}
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\DoxyCodeLine{02718\ \textcolor{preprocessor}{\#define\ \_\_ADC\_CLK\_SLEEP\_DISABLE\ \ \ \ \_\_HAL\_RCC\_ADC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02719\ \textcolor{preprocessor}{\#define\ \_\_ADC\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \_\_HAL\_RCC\_ADC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02720\ \textcolor{preprocessor}{\#define\ \_\_ADC\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC\_FORCE\_RESET}}
\DoxyCodeLine{02721\ \textcolor{preprocessor}{\#define\ \_\_ADC\_RELEASE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC\_RELEASE\_RESET}}
\DoxyCodeLine{02722\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC1\_CLK\_DISABLE}}
\DoxyCodeLine{02723\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC1\_CLK\_ENABLE}}
\DoxyCodeLine{02724\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC1\_FORCE\_RESET}}
\DoxyCodeLine{02725\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC1\_RELEASE\_RESET}}
\DoxyCodeLine{02726\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_CLK\_SLEEP\_ENABLE\ \ \ \ \_\_HAL\_RCC\_ADC1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02727\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_CLK\_SLEEP\_DISABLE\ \ \ \_\_HAL\_RCC\_ADC1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02728\ \textcolor{preprocessor}{\#define\ \_\_ADC2\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC2\_CLK\_DISABLE}}
\DoxyCodeLine{02729\ \textcolor{preprocessor}{\#define\ \_\_ADC2\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC2\_CLK\_ENABLE}}
\DoxyCodeLine{02730\ \textcolor{preprocessor}{\#define\ \_\_ADC2\_FORCE\_RESET\ \_\_HAL\_RCC\_ADC2\_FORCE\_RESET}}
\DoxyCodeLine{02731\ \textcolor{preprocessor}{\#define\ \_\_ADC2\_RELEASE\_RESET\ \_\_HAL\_RCC\_ADC2\_RELEASE\_RESET}}
\DoxyCodeLine{02732\ \textcolor{preprocessor}{\#define\ \_\_ADC3\_CLK\_DISABLE\ \_\_HAL\_RCC\_ADC3\_CLK\_DISABLE}}
\DoxyCodeLine{02733\ \textcolor{preprocessor}{\#define\ \_\_ADC3\_CLK\_ENABLE\ \_\_HAL\_RCC\_ADC3\_CLK\_ENABLE}}
\DoxyCodeLine{02734\ \textcolor{preprocessor}{\#define\ \_\_ADC3\_FORCE\_RESET\ \_\_HAL\_RCC\_ADC3\_FORCE\_RESET}}
\DoxyCodeLine{02735\ \textcolor{preprocessor}{\#define\ \_\_ADC3\_RELEASE\_RESET\ \_\_HAL\_RCC\_ADC3\_RELEASE\_RESET}}
\DoxyCodeLine{02736\ \textcolor{preprocessor}{\#define\ \_\_AES\_CLK\_DISABLE\ \_\_HAL\_RCC\_AES\_CLK\_DISABLE}}
\DoxyCodeLine{02737\ \textcolor{preprocessor}{\#define\ \_\_AES\_CLK\_ENABLE\ \_\_HAL\_RCC\_AES\_CLK\_ENABLE}}
\DoxyCodeLine{02738\ \textcolor{preprocessor}{\#define\ \_\_AES\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_AES\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02739\ \textcolor{preprocessor}{\#define\ \_\_AES\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_AES\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02740\ \textcolor{preprocessor}{\#define\ \_\_AES\_FORCE\_RESET\ \_\_HAL\_RCC\_AES\_FORCE\_RESET}}
\DoxyCodeLine{02741\ \textcolor{preprocessor}{\#define\ \_\_AES\_RELEASE\_RESET\ \_\_HAL\_RCC\_AES\_RELEASE\_RESET}}
\DoxyCodeLine{02742\ \textcolor{preprocessor}{\#define\ \_\_CRYP\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \_\_HAL\_RCC\_CRYP\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02743\ \textcolor{preprocessor}{\#define\ \_\_CRYP\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_CRYP\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02744\ \textcolor{preprocessor}{\#define\ \_\_CRYP\_CLK\_ENABLE\ \ \_\_HAL\_RCC\_CRYP\_CLK\_ENABLE}}
\DoxyCodeLine{02745\ \textcolor{preprocessor}{\#define\ \_\_CRYP\_CLK\_DISABLE\ \ \_\_HAL\_RCC\_CRYP\_CLK\_DISABLE}}
\DoxyCodeLine{02746\ \textcolor{preprocessor}{\#define\ \_\_CRYP\_FORCE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_CRYP\_FORCE\_RESET}}
\DoxyCodeLine{02747\ \textcolor{preprocessor}{\#define\ \_\_CRYP\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_CRYP\_RELEASE\_RESET}}
\DoxyCodeLine{02748\ \textcolor{preprocessor}{\#define\ \_\_AFIO\_CLK\_DISABLE\ \_\_HAL\_RCC\_AFIO\_CLK\_DISABLE}}
\DoxyCodeLine{02749\ \textcolor{preprocessor}{\#define\ \_\_AFIO\_CLK\_ENABLE\ \_\_HAL\_RCC\_AFIO\_CLK\_ENABLE}}
\DoxyCodeLine{02750\ \textcolor{preprocessor}{\#define\ \_\_AFIO\_FORCE\_RESET\ \_\_HAL\_RCC\_AFIO\_FORCE\_RESET}}
\DoxyCodeLine{02751\ \textcolor{preprocessor}{\#define\ \_\_AFIO\_RELEASE\_RESET\ \_\_HAL\_RCC\_AFIO\_RELEASE\_RESET}}
\DoxyCodeLine{02752\ \textcolor{preprocessor}{\#define\ \_\_AHB\_FORCE\_RESET\ \_\_HAL\_RCC\_AHB\_FORCE\_RESET}}
\DoxyCodeLine{02753\ \textcolor{preprocessor}{\#define\ \_\_AHB\_RELEASE\_RESET\ \_\_HAL\_RCC\_AHB\_RELEASE\_RESET}}
\DoxyCodeLine{02754\ \textcolor{preprocessor}{\#define\ \_\_AHB1\_FORCE\_RESET\ \_\_HAL\_RCC\_AHB1\_FORCE\_RESET}}
\DoxyCodeLine{02755\ \textcolor{preprocessor}{\#define\ \_\_AHB1\_RELEASE\_RESET\ \_\_HAL\_RCC\_AHB1\_RELEASE\_RESET}}
\DoxyCodeLine{02756\ \textcolor{preprocessor}{\#define\ \_\_AHB2\_FORCE\_RESET\ \_\_HAL\_RCC\_AHB2\_FORCE\_RESET}}
\DoxyCodeLine{02757\ \textcolor{preprocessor}{\#define\ \_\_AHB2\_RELEASE\_RESET\ \_\_HAL\_RCC\_AHB2\_RELEASE\_RESET}}
\DoxyCodeLine{02758\ \textcolor{preprocessor}{\#define\ \_\_AHB3\_FORCE\_RESET\ \_\_HAL\_RCC\_AHB3\_FORCE\_RESET}}
\DoxyCodeLine{02759\ \textcolor{preprocessor}{\#define\ \_\_AHB3\_RELEASE\_RESET\ \_\_HAL\_RCC\_AHB3\_RELEASE\_RESET}}
\DoxyCodeLine{02760\ \textcolor{preprocessor}{\#define\ \_\_APB1\_FORCE\_RESET\ \_\_HAL\_RCC\_APB1\_FORCE\_RESET}}
\DoxyCodeLine{02761\ \textcolor{preprocessor}{\#define\ \_\_APB1\_RELEASE\_RESET\ \_\_HAL\_RCC\_APB1\_RELEASE\_RESET}}
\DoxyCodeLine{02762\ \textcolor{preprocessor}{\#define\ \_\_APB2\_FORCE\_RESET\ \_\_HAL\_RCC\_APB2\_FORCE\_RESET}}
\DoxyCodeLine{02763\ \textcolor{preprocessor}{\#define\ \_\_APB2\_RELEASE\_RESET\ \_\_HAL\_RCC\_APB2\_RELEASE\_RESET}}
\DoxyCodeLine{02764\ \textcolor{preprocessor}{\#if\ defined(STM32C0)}}
\DoxyCodeLine{02765\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_APB1\_FORCE\_RESET\ \ \ \ \_\_HAL\_RCC\_APB1\_GRP1\_FORCE\_RESET}}
\DoxyCodeLine{02766\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_APB1\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_APB1\_GRP1\_RELEASE\_RESET}}
\DoxyCodeLine{02767\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_APB2\_FORCE\_RESET\ \ \ \ \_\_HAL\_RCC\_APB1\_GRP2\_FORCE\_RESET}}
\DoxyCodeLine{02768\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_APB2\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_APB1\_GRP2\_RELEASE\_RESET}}
\DoxyCodeLine{02769\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32C0\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02770\ \textcolor{preprocessor}{\#define\ \_\_BKP\_CLK\_DISABLE\ \_\_HAL\_RCC\_BKP\_CLK\_DISABLE}}
\DoxyCodeLine{02771\ \textcolor{preprocessor}{\#define\ \_\_BKP\_CLK\_ENABLE\ \_\_HAL\_RCC\_BKP\_CLK\_ENABLE}}
\DoxyCodeLine{02772\ \textcolor{preprocessor}{\#define\ \_\_BKP\_FORCE\_RESET\ \_\_HAL\_RCC\_BKP\_FORCE\_RESET}}
\DoxyCodeLine{02773\ \textcolor{preprocessor}{\#define\ \_\_BKP\_RELEASE\_RESET\ \_\_HAL\_RCC\_BKP\_RELEASE\_RESET}}
\DoxyCodeLine{02774\ \textcolor{preprocessor}{\#define\ \_\_CAN1\_CLK\_DISABLE\ \_\_HAL\_RCC\_CAN1\_CLK\_DISABLE}}
\DoxyCodeLine{02775\ \textcolor{preprocessor}{\#define\ \_\_CAN1\_CLK\_ENABLE\ \_\_HAL\_RCC\_CAN1\_CLK\_ENABLE}}
\DoxyCodeLine{02776\ \textcolor{preprocessor}{\#define\ \_\_CAN1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_CAN1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02777\ \textcolor{preprocessor}{\#define\ \_\_CAN1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_CAN1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02778\ \textcolor{preprocessor}{\#define\ \_\_CAN1\_FORCE\_RESET\ \_\_HAL\_RCC\_CAN1\_FORCE\_RESET}}
\DoxyCodeLine{02779\ \textcolor{preprocessor}{\#define\ \_\_CAN1\_RELEASE\_RESET\ \_\_HAL\_RCC\_CAN1\_RELEASE\_RESET}}
\DoxyCodeLine{02780\ \textcolor{preprocessor}{\#define\ \_\_CAN\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_CAN1\_CLK\_DISABLE}}
\DoxyCodeLine{02781\ \textcolor{preprocessor}{\#define\ \_\_CAN\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_CAN1\_CLK\_ENABLE}}
\DoxyCodeLine{02782\ \textcolor{preprocessor}{\#define\ \_\_CAN\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_CAN1\_FORCE\_RESET}}
\DoxyCodeLine{02783\ \textcolor{preprocessor}{\#define\ \_\_CAN\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_CAN1\_RELEASE\_RESET}}
\DoxyCodeLine{02784\ \textcolor{preprocessor}{\#define\ \_\_CAN2\_CLK\_DISABLE\ \_\_HAL\_RCC\_CAN2\_CLK\_DISABLE}}
\DoxyCodeLine{02785\ \textcolor{preprocessor}{\#define\ \_\_CAN2\_CLK\_ENABLE\ \_\_HAL\_RCC\_CAN2\_CLK\_ENABLE}}
\DoxyCodeLine{02786\ \textcolor{preprocessor}{\#define\ \_\_CAN2\_FORCE\_RESET\ \_\_HAL\_RCC\_CAN2\_FORCE\_RESET}}
\DoxyCodeLine{02787\ \textcolor{preprocessor}{\#define\ \_\_CAN2\_RELEASE\_RESET\ \_\_HAL\_RCC\_CAN2\_RELEASE\_RESET}}
\DoxyCodeLine{02788\ \textcolor{preprocessor}{\#define\ \_\_CEC\_CLK\_DISABLE\ \_\_HAL\_RCC\_CEC\_CLK\_DISABLE}}
\DoxyCodeLine{02789\ \textcolor{preprocessor}{\#define\ \_\_CEC\_CLK\_ENABLE\ \_\_HAL\_RCC\_CEC\_CLK\_ENABLE}}
\DoxyCodeLine{02790\ \textcolor{preprocessor}{\#define\ \_\_COMP\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_COMP\_CLK\_DISABLE}}
\DoxyCodeLine{02791\ \textcolor{preprocessor}{\#define\ \_\_COMP\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_COMP\_CLK\_ENABLE}}
\DoxyCodeLine{02792\ \textcolor{preprocessor}{\#define\ \_\_COMP\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_COMP\_FORCE\_RESET}}
\DoxyCodeLine{02793\ \textcolor{preprocessor}{\#define\ \_\_COMP\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_COMP\_RELEASE\_RESET}}
\DoxyCodeLine{02794\ \textcolor{preprocessor}{\#define\ \_\_COMP\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_COMP\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02795\ \textcolor{preprocessor}{\#define\ \_\_COMP\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_COMP\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02796\ \textcolor{preprocessor}{\#define\ \_\_CEC\_FORCE\_RESET\ \_\_HAL\_RCC\_CEC\_FORCE\_RESET}}
\DoxyCodeLine{02797\ \textcolor{preprocessor}{\#define\ \_\_CEC\_RELEASE\_RESET\ \_\_HAL\_RCC\_CEC\_RELEASE\_RESET}}
\DoxyCodeLine{02798\ \textcolor{preprocessor}{\#define\ \_\_CRC\_CLK\_DISABLE\ \_\_HAL\_RCC\_CRC\_CLK\_DISABLE}}
\DoxyCodeLine{02799\ \textcolor{preprocessor}{\#define\ \_\_CRC\_CLK\_ENABLE\ \_\_HAL\_RCC\_CRC\_CLK\_ENABLE}}
\DoxyCodeLine{02800\ \textcolor{preprocessor}{\#define\ \_\_CRC\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_CRC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02801\ \textcolor{preprocessor}{\#define\ \_\_CRC\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_CRC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02802\ \textcolor{preprocessor}{\#define\ \_\_CRC\_FORCE\_RESET\ \_\_HAL\_RCC\_CRC\_FORCE\_RESET}}
\DoxyCodeLine{02803\ \textcolor{preprocessor}{\#define\ \_\_CRC\_RELEASE\_RESET\ \_\_HAL\_RCC\_CRC\_RELEASE\_RESET}}
\DoxyCodeLine{02804\ \textcolor{preprocessor}{\#define\ \_\_DAC\_CLK\_DISABLE\ \_\_HAL\_RCC\_DAC\_CLK\_DISABLE}}
\DoxyCodeLine{02805\ \textcolor{preprocessor}{\#define\ \_\_DAC\_CLK\_ENABLE\ \_\_HAL\_RCC\_DAC\_CLK\_ENABLE}}
\DoxyCodeLine{02806\ \textcolor{preprocessor}{\#define\ \_\_DAC\_FORCE\_RESET\ \_\_HAL\_RCC\_DAC\_FORCE\_RESET}}
\DoxyCodeLine{02807\ \textcolor{preprocessor}{\#define\ \_\_DAC\_RELEASE\_RESET\ \_\_HAL\_RCC\_DAC\_RELEASE\_RESET}}
\DoxyCodeLine{02808\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_CLK\_DISABLE\ \_\_HAL\_RCC\_DAC1\_CLK\_DISABLE}}
\DoxyCodeLine{02809\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_CLK\_ENABLE\ \_\_HAL\_RCC\_DAC1\_CLK\_ENABLE}}
\DoxyCodeLine{02810\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_DAC1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02811\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_DAC1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02812\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_FORCE\_RESET\ \_\_HAL\_RCC\_DAC1\_FORCE\_RESET}}
\DoxyCodeLine{02813\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_RELEASE\_RESET\ \_\_HAL\_RCC\_DAC1\_RELEASE\_RESET}}
\DoxyCodeLine{02814\ \textcolor{preprocessor}{\#define\ \_\_DBGMCU\_CLK\_ENABLE\ \ \ \ \ \_\_HAL\_RCC\_DBGMCU\_CLK\_ENABLE}}
\DoxyCodeLine{02815\ \textcolor{preprocessor}{\#define\ \_\_DBGMCU\_CLK\_DISABLE\ \ \ \ \ \_\_HAL\_RCC\_DBGMCU\_CLK\_DISABLE}}
\DoxyCodeLine{02816\ \textcolor{preprocessor}{\#define\ \_\_DBGMCU\_FORCE\_RESET\ \ \ \ \_\_HAL\_RCC\_DBGMCU\_FORCE\_RESET}}
\DoxyCodeLine{02817\ \textcolor{preprocessor}{\#define\ \_\_DBGMCU\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_DBGMCU\_RELEASE\_RESET}}
\DoxyCodeLine{02818\ \textcolor{preprocessor}{\#define\ \_\_DFSDM\_CLK\_DISABLE\ \_\_HAL\_RCC\_DFSDM\_CLK\_DISABLE}}
\DoxyCodeLine{02819\ \textcolor{preprocessor}{\#define\ \_\_DFSDM\_CLK\_ENABLE\ \_\_HAL\_RCC\_DFSDM\_CLK\_ENABLE}}
\DoxyCodeLine{02820\ \textcolor{preprocessor}{\#define\ \_\_DFSDM\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_DFSDM\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02821\ \textcolor{preprocessor}{\#define\ \_\_DFSDM\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_DFSDM\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02822\ \textcolor{preprocessor}{\#define\ \_\_DFSDM\_FORCE\_RESET\ \_\_HAL\_RCC\_DFSDM\_FORCE\_RESET}}
\DoxyCodeLine{02823\ \textcolor{preprocessor}{\#define\ \_\_DFSDM\_RELEASE\_RESET\ \_\_HAL\_RCC\_DFSDM\_RELEASE\_RESET}}
\DoxyCodeLine{02824\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_CLK\_DISABLE\ \_\_HAL\_RCC\_DMA1\_CLK\_DISABLE}}
\DoxyCodeLine{02825\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_CLK\_ENABLE\ \_\_HAL\_RCC\_DMA1\_CLK\_ENABLE}}
\DoxyCodeLine{02826\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_DMA1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02827\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_DMA1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02828\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_FORCE\_RESET\ \_\_HAL\_RCC\_DMA1\_FORCE\_RESET}}
\DoxyCodeLine{02829\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_RELEASE\_RESET\ \_\_HAL\_RCC\_DMA1\_RELEASE\_RESET}}
\DoxyCodeLine{02830\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_CLK\_DISABLE\ \_\_HAL\_RCC\_DMA2\_CLK\_DISABLE}}
\DoxyCodeLine{02831\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_CLK\_ENABLE\ \_\_HAL\_RCC\_DMA2\_CLK\_ENABLE}}
\DoxyCodeLine{02832\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_DMA2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02833\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_DMA2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02834\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_FORCE\_RESET\ \_\_HAL\_RCC\_DMA2\_FORCE\_RESET}}
\DoxyCodeLine{02835\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_RELEASE\_RESET\ \_\_HAL\_RCC\_DMA2\_RELEASE\_RESET}}
\DoxyCodeLine{02836\ \textcolor{preprocessor}{\#define\ \_\_ETHMAC\_CLK\_DISABLE\ \_\_HAL\_RCC\_ETHMAC\_CLK\_DISABLE}}
\DoxyCodeLine{02837\ \textcolor{preprocessor}{\#define\ \_\_ETHMAC\_CLK\_ENABLE\ \_\_HAL\_RCC\_ETHMAC\_CLK\_ENABLE}}
\DoxyCodeLine{02838\ \textcolor{preprocessor}{\#define\ \_\_ETHMAC\_FORCE\_RESET\ \_\_HAL\_RCC\_ETHMAC\_FORCE\_RESET}}
\DoxyCodeLine{02839\ \textcolor{preprocessor}{\#define\ \_\_ETHMAC\_RELEASE\_RESET\ \_\_HAL\_RCC\_ETHMAC\_RELEASE\_RESET}}
\DoxyCodeLine{02840\ \textcolor{preprocessor}{\#define\ \_\_ETHMACRX\_CLK\_DISABLE\ \_\_HAL\_RCC\_ETHMACRX\_CLK\_DISABLE}}
\DoxyCodeLine{02841\ \textcolor{preprocessor}{\#define\ \_\_ETHMACRX\_CLK\_ENABLE\ \_\_HAL\_RCC\_ETHMACRX\_CLK\_ENABLE}}
\DoxyCodeLine{02842\ \textcolor{preprocessor}{\#define\ \_\_ETHMACTX\_CLK\_DISABLE\ \_\_HAL\_RCC\_ETHMACTX\_CLK\_DISABLE}}
\DoxyCodeLine{02843\ \textcolor{preprocessor}{\#define\ \_\_ETHMACTX\_CLK\_ENABLE\ \_\_HAL\_RCC\_ETHMACTX\_CLK\_ENABLE}}
\DoxyCodeLine{02844\ \textcolor{preprocessor}{\#define\ \_\_FIREWALL\_CLK\_DISABLE\ \_\_HAL\_RCC\_FIREWALL\_CLK\_DISABLE}}
\DoxyCodeLine{02845\ \textcolor{preprocessor}{\#define\ \_\_FIREWALL\_CLK\_ENABLE\ \_\_HAL\_RCC\_FIREWALL\_CLK\_ENABLE}}
\DoxyCodeLine{02846\ \textcolor{preprocessor}{\#define\ \_\_FLASH\_CLK\_DISABLE\ \_\_HAL\_RCC\_FLASH\_CLK\_DISABLE}}
\DoxyCodeLine{02847\ \textcolor{preprocessor}{\#define\ \_\_FLASH\_CLK\_ENABLE\ \_\_HAL\_RCC\_FLASH\_CLK\_ENABLE}}
\DoxyCodeLine{02848\ \textcolor{preprocessor}{\#define\ \_\_FLASH\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_FLASH\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02849\ \textcolor{preprocessor}{\#define\ \_\_FLASH\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_FLASH\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02850\ \textcolor{preprocessor}{\#define\ \_\_FLASH\_FORCE\_RESET\ \_\_HAL\_RCC\_FLASH\_FORCE\_RESET}}
\DoxyCodeLine{02851\ \textcolor{preprocessor}{\#define\ \_\_FLASH\_RELEASE\_RESET\ \_\_HAL\_RCC\_FLASH\_RELEASE\_RESET}}
\DoxyCodeLine{02852\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_CLK\_DISABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_FLITF\_CLK\_DISABLE}}
\DoxyCodeLine{02853\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_CLK\_ENABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_FLITF\_CLK\_ENABLE}}
\DoxyCodeLine{02854\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_FORCE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_FLITF\_FORCE\_RESET}}
\DoxyCodeLine{02855\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_RELEASE\_RESET\ \ \ \ \ \_\_HAL\_RCC\_FLITF\_RELEASE\_RESET}}
\DoxyCodeLine{02856\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_FLITF\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02857\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_FLITF\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02858\ \textcolor{preprocessor}{\#define\ \_\_FMC\_CLK\_DISABLE\ \_\_HAL\_RCC\_FMC\_CLK\_DISABLE}}
\DoxyCodeLine{02859\ \textcolor{preprocessor}{\#define\ \_\_FMC\_CLK\_ENABLE\ \_\_HAL\_RCC\_FMC\_CLK\_ENABLE}}
\DoxyCodeLine{02860\ \textcolor{preprocessor}{\#define\ \_\_FMC\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_FMC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02861\ \textcolor{preprocessor}{\#define\ \_\_FMC\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_FMC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02862\ \textcolor{preprocessor}{\#define\ \_\_FMC\_FORCE\_RESET\ \_\_HAL\_RCC\_FMC\_FORCE\_RESET}}
\DoxyCodeLine{02863\ \textcolor{preprocessor}{\#define\ \_\_FMC\_RELEASE\_RESET\ \_\_HAL\_RCC\_FMC\_RELEASE\_RESET}}
\DoxyCodeLine{02864\ \textcolor{preprocessor}{\#define\ \_\_FSMC\_CLK\_DISABLE\ \_\_HAL\_RCC\_FSMC\_CLK\_DISABLE}}
\DoxyCodeLine{02865\ \textcolor{preprocessor}{\#define\ \_\_FSMC\_CLK\_ENABLE\ \_\_HAL\_RCC\_FSMC\_CLK\_ENABLE}}
\DoxyCodeLine{02866\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOA\_CLK\_DISABLE}}
\DoxyCodeLine{02867\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOA\_CLK\_ENABLE}}
\DoxyCodeLine{02868\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOA\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02869\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOA\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02870\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOA\_FORCE\_RESET}}
\DoxyCodeLine{02871\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOA\_RELEASE\_RESET}}
\DoxyCodeLine{02872\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOB\_CLK\_DISABLE}}
\DoxyCodeLine{02873\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOB\_CLK\_ENABLE}}
\DoxyCodeLine{02874\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOB\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02875\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOB\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02876\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOB\_FORCE\_RESET}}
\DoxyCodeLine{02877\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOB\_RELEASE\_RESET}}
\DoxyCodeLine{02878\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOC\_CLK\_DISABLE}}
\DoxyCodeLine{02879\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOC\_CLK\_ENABLE}}
\DoxyCodeLine{02880\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02881\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02882\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOC\_FORCE\_RESET}}
\DoxyCodeLine{02883\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOC\_RELEASE\_RESET}}
\DoxyCodeLine{02884\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOD\_CLK\_DISABLE}}
\DoxyCodeLine{02885\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOD\_CLK\_ENABLE}}
\DoxyCodeLine{02886\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOD\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02887\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOD\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02888\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOD\_FORCE\_RESET}}
\DoxyCodeLine{02889\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOD\_RELEASE\_RESET}}
\DoxyCodeLine{02890\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOE\_CLK\_DISABLE}}
\DoxyCodeLine{02891\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOE\_CLK\_ENABLE}}
\DoxyCodeLine{02892\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOE\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02893\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOE\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02894\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOE\_FORCE\_RESET}}
\DoxyCodeLine{02895\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOE\_RELEASE\_RESET}}
\DoxyCodeLine{02896\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOF\_CLK\_DISABLE}}
\DoxyCodeLine{02897\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOF\_CLK\_ENABLE}}
\DoxyCodeLine{02898\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOF\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02899\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOF\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02900\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOF\_FORCE\_RESET}}
\DoxyCodeLine{02901\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOF\_RELEASE\_RESET}}
\DoxyCodeLine{02902\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOG\_CLK\_DISABLE}}
\DoxyCodeLine{02903\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOG\_CLK\_ENABLE}}
\DoxyCodeLine{02904\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOG\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02905\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOG\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02906\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOG\_FORCE\_RESET}}
\DoxyCodeLine{02907\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOG\_RELEASE\_RESET}}
\DoxyCodeLine{02908\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_CLK\_DISABLE\ \_\_HAL\_RCC\_GPIOH\_CLK\_DISABLE}}
\DoxyCodeLine{02909\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_CLK\_ENABLE\ \_\_HAL\_RCC\_GPIOH\_CLK\_ENABLE}}
\DoxyCodeLine{02910\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_GPIOH\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02911\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_GPIOH\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02912\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_FORCE\_RESET\ \_\_HAL\_RCC\_GPIOH\_FORCE\_RESET}}
\DoxyCodeLine{02913\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_RELEASE\_RESET\ \_\_HAL\_RCC\_GPIOH\_RELEASE\_RESET}}
\DoxyCodeLine{02914\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_CLK\_DISABLE\ \_\_HAL\_RCC\_I2C1\_CLK\_DISABLE}}
\DoxyCodeLine{02915\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_CLK\_ENABLE\ \_\_HAL\_RCC\_I2C1\_CLK\_ENABLE}}
\DoxyCodeLine{02916\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_I2C1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02917\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_I2C1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02918\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_FORCE\_RESET\ \_\_HAL\_RCC\_I2C1\_FORCE\_RESET}}
\DoxyCodeLine{02919\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_RELEASE\_RESET\ \_\_HAL\_RCC\_I2C1\_RELEASE\_RESET}}
\DoxyCodeLine{02920\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_CLK\_DISABLE\ \_\_HAL\_RCC\_I2C2\_CLK\_DISABLE}}
\DoxyCodeLine{02921\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_CLK\_ENABLE\ \_\_HAL\_RCC\_I2C2\_CLK\_ENABLE}}
\DoxyCodeLine{02922\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_I2C2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02923\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_I2C2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02924\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_FORCE\_RESET\ \_\_HAL\_RCC\_I2C2\_FORCE\_RESET}}
\DoxyCodeLine{02925\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_RELEASE\_RESET\ \_\_HAL\_RCC\_I2C2\_RELEASE\_RESET}}
\DoxyCodeLine{02926\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_CLK\_DISABLE\ \_\_HAL\_RCC\_I2C3\_CLK\_DISABLE}}
\DoxyCodeLine{02927\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_CLK\_ENABLE\ \_\_HAL\_RCC\_I2C3\_CLK\_ENABLE}}
\DoxyCodeLine{02928\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_I2C3\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02929\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_I2C3\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02930\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_FORCE\_RESET\ \_\_HAL\_RCC\_I2C3\_FORCE\_RESET}}
\DoxyCodeLine{02931\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_RELEASE\_RESET\ \_\_HAL\_RCC\_I2C3\_RELEASE\_RESET}}
\DoxyCodeLine{02932\ \textcolor{preprocessor}{\#define\ \_\_LCD\_CLK\_DISABLE\ \_\_HAL\_RCC\_LCD\_CLK\_DISABLE}}
\DoxyCodeLine{02933\ \textcolor{preprocessor}{\#define\ \_\_LCD\_CLK\_ENABLE\ \_\_HAL\_RCC\_LCD\_CLK\_ENABLE}}
\DoxyCodeLine{02934\ \textcolor{preprocessor}{\#define\ \_\_LCD\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_LCD\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02935\ \textcolor{preprocessor}{\#define\ \_\_LCD\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_LCD\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02936\ \textcolor{preprocessor}{\#define\ \_\_LCD\_FORCE\_RESET\ \_\_HAL\_RCC\_LCD\_FORCE\_RESET}}
\DoxyCodeLine{02937\ \textcolor{preprocessor}{\#define\ \_\_LCD\_RELEASE\_RESET\ \_\_HAL\_RCC\_LCD\_RELEASE\_RESET}}
\DoxyCodeLine{02938\ \textcolor{preprocessor}{\#define\ \_\_LPTIM1\_CLK\_DISABLE\ \_\_HAL\_RCC\_LPTIM1\_CLK\_DISABLE}}
\DoxyCodeLine{02939\ \textcolor{preprocessor}{\#define\ \_\_LPTIM1\_CLK\_ENABLE\ \_\_HAL\_RCC\_LPTIM1\_CLK\_ENABLE}}
\DoxyCodeLine{02940\ \textcolor{preprocessor}{\#define\ \_\_LPTIM1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_LPTIM1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02941\ \textcolor{preprocessor}{\#define\ \_\_LPTIM1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_LPTIM1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02942\ \textcolor{preprocessor}{\#define\ \_\_LPTIM1\_FORCE\_RESET\ \_\_HAL\_RCC\_LPTIM1\_FORCE\_RESET}}
\DoxyCodeLine{02943\ \textcolor{preprocessor}{\#define\ \_\_LPTIM1\_RELEASE\_RESET\ \_\_HAL\_RCC\_LPTIM1\_RELEASE\_RESET}}
\DoxyCodeLine{02944\ \textcolor{preprocessor}{\#define\ \_\_LPTIM2\_CLK\_DISABLE\ \_\_HAL\_RCC\_LPTIM2\_CLK\_DISABLE}}
\DoxyCodeLine{02945\ \textcolor{preprocessor}{\#define\ \_\_LPTIM2\_CLK\_ENABLE\ \_\_HAL\_RCC\_LPTIM2\_CLK\_ENABLE}}
\DoxyCodeLine{02946\ \textcolor{preprocessor}{\#define\ \_\_LPTIM2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_LPTIM2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02947\ \textcolor{preprocessor}{\#define\ \_\_LPTIM2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_LPTIM2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02948\ \textcolor{preprocessor}{\#define\ \_\_LPTIM2\_FORCE\_RESET\ \_\_HAL\_RCC\_LPTIM2\_FORCE\_RESET}}
\DoxyCodeLine{02949\ \textcolor{preprocessor}{\#define\ \_\_LPTIM2\_RELEASE\_RESET\ \_\_HAL\_RCC\_LPTIM2\_RELEASE\_RESET}}
\DoxyCodeLine{02950\ \textcolor{preprocessor}{\#define\ \_\_LPUART1\_CLK\_DISABLE\ \_\_HAL\_RCC\_LPUART1\_CLK\_DISABLE}}
\DoxyCodeLine{02951\ \textcolor{preprocessor}{\#define\ \_\_LPUART1\_CLK\_ENABLE\ \_\_HAL\_RCC\_LPUART1\_CLK\_ENABLE}}
\DoxyCodeLine{02952\ \textcolor{preprocessor}{\#define\ \_\_LPUART1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_LPUART1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02953\ \textcolor{preprocessor}{\#define\ \_\_LPUART1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_LPUART1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02954\ \textcolor{preprocessor}{\#define\ \_\_LPUART1\_FORCE\_RESET\ \_\_HAL\_RCC\_LPUART1\_FORCE\_RESET}}
\DoxyCodeLine{02955\ \textcolor{preprocessor}{\#define\ \_\_LPUART1\_RELEASE\_RESET\ \_\_HAL\_RCC\_LPUART1\_RELEASE\_RESET}}
\DoxyCodeLine{02956\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_CLK\_DISABLE\ \_\_HAL\_RCC\_OPAMP\_CLK\_DISABLE}}
\DoxyCodeLine{02957\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_CLK\_ENABLE\ \_\_HAL\_RCC\_OPAMP\_CLK\_ENABLE}}
\DoxyCodeLine{02958\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_OPAMP\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02959\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_OPAMP\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02960\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_FORCE\_RESET\ \_\_HAL\_RCC\_OPAMP\_FORCE\_RESET}}
\DoxyCodeLine{02961\ \textcolor{preprocessor}{\#define\ \_\_OPAMP\_RELEASE\_RESET\ \_\_HAL\_RCC\_OPAMP\_RELEASE\_RESET}}
\DoxyCodeLine{02962\ \textcolor{preprocessor}{\#define\ \_\_OTGFS\_CLK\_DISABLE\ \_\_HAL\_RCC\_OTGFS\_CLK\_DISABLE}}
\DoxyCodeLine{02963\ \textcolor{preprocessor}{\#define\ \_\_OTGFS\_CLK\_ENABLE\ \_\_HAL\_RCC\_OTGFS\_CLK\_ENABLE}}
\DoxyCodeLine{02964\ \textcolor{preprocessor}{\#define\ \_\_OTGFS\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_OTGFS\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02965\ \textcolor{preprocessor}{\#define\ \_\_OTGFS\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_OTGFS\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02966\ \textcolor{preprocessor}{\#define\ \_\_OTGFS\_FORCE\_RESET\ \_\_HAL\_RCC\_OTGFS\_FORCE\_RESET}}
\DoxyCodeLine{02967\ \textcolor{preprocessor}{\#define\ \_\_OTGFS\_RELEASE\_RESET\ \_\_HAL\_RCC\_OTGFS\_RELEASE\_RESET}}
\DoxyCodeLine{02968\ \textcolor{preprocessor}{\#define\ \_\_PWR\_CLK\_DISABLE\ \_\_HAL\_RCC\_PWR\_CLK\_DISABLE}}
\DoxyCodeLine{02969\ \textcolor{preprocessor}{\#define\ \_\_PWR\_CLK\_ENABLE\ \_\_HAL\_RCC\_PWR\_CLK\_ENABLE}}
\DoxyCodeLine{02970\ \textcolor{preprocessor}{\#define\ \_\_PWR\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_PWR\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02971\ \textcolor{preprocessor}{\#define\ \_\_PWR\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_PWR\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02972\ \textcolor{preprocessor}{\#define\ \_\_PWR\_FORCE\_RESET\ \_\_HAL\_RCC\_PWR\_FORCE\_RESET}}
\DoxyCodeLine{02973\ \textcolor{preprocessor}{\#define\ \_\_PWR\_RELEASE\_RESET\ \_\_HAL\_RCC\_PWR\_RELEASE\_RESET}}
\DoxyCodeLine{02974\ \textcolor{preprocessor}{\#define\ \_\_QSPI\_CLK\_DISABLE\ \_\_HAL\_RCC\_QSPI\_CLK\_DISABLE}}
\DoxyCodeLine{02975\ \textcolor{preprocessor}{\#define\ \_\_QSPI\_CLK\_ENABLE\ \_\_HAL\_RCC\_QSPI\_CLK\_ENABLE}}
\DoxyCodeLine{02976\ \textcolor{preprocessor}{\#define\ \_\_QSPI\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_QSPI\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02977\ \textcolor{preprocessor}{\#define\ \_\_QSPI\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_QSPI\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02978\ \textcolor{preprocessor}{\#define\ \_\_QSPI\_FORCE\_RESET\ \_\_HAL\_RCC\_QSPI\_FORCE\_RESET}}
\DoxyCodeLine{02979\ \textcolor{preprocessor}{\#define\ \_\_QSPI\_RELEASE\_RESET\ \_\_HAL\_RCC\_QSPI\_RELEASE\_RESET}}
\DoxyCodeLine{02980\ }
\DoxyCodeLine{02981\ \textcolor{preprocessor}{\#if\ defined(STM32WB)}}
\DoxyCodeLine{02982\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_CLK\_DISABLE}}
\DoxyCodeLine{02983\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_CLK\_ENABLE}}
\DoxyCodeLine{02984\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02985\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02986\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_FORCE\_RESET}}
\DoxyCodeLine{02987\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_RELEASE\_RESET}}
\DoxyCodeLine{02988\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{02989\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_IS\_CLK\_DISABLED\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_QUADSPI\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{02990\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_IS\_CLK\_SLEEP\_ENABLED\ \ \ \_\_HAL\_RCC\_QUADSPI\_IS\_CLK\_SLEEP\_ENABLED}}
\DoxyCodeLine{02991\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_QSPI\_IS\_CLK\_SLEEP\_DISABLED\ \ \_\_HAL\_RCC\_QUADSPI\_IS\_CLK\_SLEEP\_DISABLED}}
\DoxyCodeLine{02992\ \textcolor{preprocessor}{\#define\ QSPI\_IRQHandler\ QUADSPI\_IRQHandler}}
\DoxyCodeLine{02993\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_HAL\_RCC\_QUADSPI\_CLK\_ENABLE\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{02994\ }
\DoxyCodeLine{02995\ \textcolor{preprocessor}{\#define\ \_\_RNG\_CLK\_DISABLE\ \_\_HAL\_RCC\_RNG\_CLK\_DISABLE}}
\DoxyCodeLine{02996\ \textcolor{preprocessor}{\#define\ \_\_RNG\_CLK\_ENABLE\ \_\_HAL\_RCC\_RNG\_CLK\_ENABLE}}
\DoxyCodeLine{02997\ \textcolor{preprocessor}{\#define\ \_\_RNG\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_RNG\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{02998\ \textcolor{preprocessor}{\#define\ \_\_RNG\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_RNG\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{02999\ \textcolor{preprocessor}{\#define\ \_\_RNG\_FORCE\_RESET\ \_\_HAL\_RCC\_RNG\_FORCE\_RESET}}
\DoxyCodeLine{03000\ \textcolor{preprocessor}{\#define\ \_\_RNG\_RELEASE\_RESET\ \_\_HAL\_RCC\_RNG\_RELEASE\_RESET}}
\DoxyCodeLine{03001\ \textcolor{preprocessor}{\#define\ \_\_SAI1\_CLK\_DISABLE\ \_\_HAL\_RCC\_SAI1\_CLK\_DISABLE}}
\DoxyCodeLine{03002\ \textcolor{preprocessor}{\#define\ \_\_SAI1\_CLK\_ENABLE\ \_\_HAL\_RCC\_SAI1\_CLK\_ENABLE}}
\DoxyCodeLine{03003\ \textcolor{preprocessor}{\#define\ \_\_SAI1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SAI1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03004\ \textcolor{preprocessor}{\#define\ \_\_SAI1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SAI1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03005\ \textcolor{preprocessor}{\#define\ \_\_SAI1\_FORCE\_RESET\ \_\_HAL\_RCC\_SAI1\_FORCE\_RESET}}
\DoxyCodeLine{03006\ \textcolor{preprocessor}{\#define\ \_\_SAI1\_RELEASE\_RESET\ \_\_HAL\_RCC\_SAI1\_RELEASE\_RESET}}
\DoxyCodeLine{03007\ \textcolor{preprocessor}{\#define\ \_\_SAI2\_CLK\_DISABLE\ \_\_HAL\_RCC\_SAI2\_CLK\_DISABLE}}
\DoxyCodeLine{03008\ \textcolor{preprocessor}{\#define\ \_\_SAI2\_CLK\_ENABLE\ \_\_HAL\_RCC\_SAI2\_CLK\_ENABLE}}
\DoxyCodeLine{03009\ \textcolor{preprocessor}{\#define\ \_\_SAI2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SAI2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03010\ \textcolor{preprocessor}{\#define\ \_\_SAI2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SAI2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03011\ \textcolor{preprocessor}{\#define\ \_\_SAI2\_FORCE\_RESET\ \_\_HAL\_RCC\_SAI2\_FORCE\_RESET}}
\DoxyCodeLine{03012\ \textcolor{preprocessor}{\#define\ \_\_SAI2\_RELEASE\_RESET\ \_\_HAL\_RCC\_SAI2\_RELEASE\_RESET}}
\DoxyCodeLine{03013\ \textcolor{preprocessor}{\#define\ \_\_SDIO\_CLK\_DISABLE\ \_\_HAL\_RCC\_SDIO\_CLK\_DISABLE}}
\DoxyCodeLine{03014\ \textcolor{preprocessor}{\#define\ \_\_SDIO\_CLK\_ENABLE\ \_\_HAL\_RCC\_SDIO\_CLK\_ENABLE}}
\DoxyCodeLine{03015\ \textcolor{preprocessor}{\#define\ \_\_SDMMC\_CLK\_DISABLE\ \_\_HAL\_RCC\_SDMMC\_CLK\_DISABLE}}
\DoxyCodeLine{03016\ \textcolor{preprocessor}{\#define\ \_\_SDMMC\_CLK\_ENABLE\ \_\_HAL\_RCC\_SDMMC\_CLK\_ENABLE}}
\DoxyCodeLine{03017\ \textcolor{preprocessor}{\#define\ \_\_SDMMC\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SDMMC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03018\ \textcolor{preprocessor}{\#define\ \_\_SDMMC\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SDMMC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03019\ \textcolor{preprocessor}{\#define\ \_\_SDMMC\_FORCE\_RESET\ \_\_HAL\_RCC\_SDMMC\_FORCE\_RESET}}
\DoxyCodeLine{03020\ \textcolor{preprocessor}{\#define\ \_\_SDMMC\_RELEASE\_RESET\ \_\_HAL\_RCC\_SDMMC\_RELEASE\_RESET}}
\DoxyCodeLine{03021\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_CLK\_DISABLE\ \_\_HAL\_RCC\_SPI1\_CLK\_DISABLE}}
\DoxyCodeLine{03022\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_CLK\_ENABLE\ \_\_HAL\_RCC\_SPI1\_CLK\_ENABLE}}
\DoxyCodeLine{03023\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SPI1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03024\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SPI1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03025\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_FORCE\_RESET\ \_\_HAL\_RCC\_SPI1\_FORCE\_RESET}}
\DoxyCodeLine{03026\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_RELEASE\_RESET\ \_\_HAL\_RCC\_SPI1\_RELEASE\_RESET}}
\DoxyCodeLine{03027\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_CLK\_DISABLE\ \_\_HAL\_RCC\_SPI2\_CLK\_DISABLE}}
\DoxyCodeLine{03028\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_CLK\_ENABLE\ \_\_HAL\_RCC\_SPI2\_CLK\_ENABLE}}
\DoxyCodeLine{03029\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SPI2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03030\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SPI2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03031\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_FORCE\_RESET\ \_\_HAL\_RCC\_SPI2\_FORCE\_RESET}}
\DoxyCodeLine{03032\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_RELEASE\_RESET\ \_\_HAL\_RCC\_SPI2\_RELEASE\_RESET}}
\DoxyCodeLine{03033\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_CLK\_DISABLE\ \_\_HAL\_RCC\_SPI3\_CLK\_DISABLE}}
\DoxyCodeLine{03034\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_CLK\_ENABLE\ \_\_HAL\_RCC\_SPI3\_CLK\_ENABLE}}
\DoxyCodeLine{03035\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SPI3\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03036\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SPI3\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03037\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_FORCE\_RESET\ \_\_HAL\_RCC\_SPI3\_FORCE\_RESET}}
\DoxyCodeLine{03038\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_RELEASE\_RESET\ \_\_HAL\_RCC\_SPI3\_RELEASE\_RESET}}
\DoxyCodeLine{03039\ \textcolor{preprocessor}{\#define\ \_\_SRAM\_CLK\_DISABLE\ \_\_HAL\_RCC\_SRAM\_CLK\_DISABLE}}
\DoxyCodeLine{03040\ \textcolor{preprocessor}{\#define\ \_\_SRAM\_CLK\_ENABLE\ \_\_HAL\_RCC\_SRAM\_CLK\_ENABLE}}
\DoxyCodeLine{03041\ \textcolor{preprocessor}{\#define\ \_\_SRAM1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SRAM1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03042\ \textcolor{preprocessor}{\#define\ \_\_SRAM1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SRAM1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03043\ \textcolor{preprocessor}{\#define\ \_\_SRAM2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SRAM2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03044\ \textcolor{preprocessor}{\#define\ \_\_SRAM2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SRAM2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03045\ \textcolor{preprocessor}{\#define\ \_\_SWPMI1\_CLK\_DISABLE\ \_\_HAL\_RCC\_SWPMI1\_CLK\_DISABLE}}
\DoxyCodeLine{03046\ \textcolor{preprocessor}{\#define\ \_\_SWPMI1\_CLK\_ENABLE\ \_\_HAL\_RCC\_SWPMI1\_CLK\_ENABLE}}
\DoxyCodeLine{03047\ \textcolor{preprocessor}{\#define\ \_\_SWPMI1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SWPMI1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03048\ \textcolor{preprocessor}{\#define\ \_\_SWPMI1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SWPMI1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03049\ \textcolor{preprocessor}{\#define\ \_\_SWPMI1\_FORCE\_RESET\ \_\_HAL\_RCC\_SWPMI1\_FORCE\_RESET}}
\DoxyCodeLine{03050\ \textcolor{preprocessor}{\#define\ \_\_SWPMI1\_RELEASE\_RESET\ \_\_HAL\_RCC\_SWPMI1\_RELEASE\_RESET}}
\DoxyCodeLine{03051\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_CLK\_DISABLE\ \_\_HAL\_RCC\_SYSCFG\_CLK\_DISABLE}}
\DoxyCodeLine{03052\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_CLK\_ENABLE\ \_\_HAL\_RCC\_SYSCFG\_CLK\_ENABLE}}
\DoxyCodeLine{03053\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_SYSCFG\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03054\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_SYSCFG\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03055\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_FORCE\_RESET\ \_\_HAL\_RCC\_SYSCFG\_FORCE\_RESET}}
\DoxyCodeLine{03056\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_RELEASE\_RESET\ \_\_HAL\_RCC\_SYSCFG\_RELEASE\_RESET}}
\DoxyCodeLine{03057\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM1\_CLK\_DISABLE}}
\DoxyCodeLine{03058\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM1\_CLK\_ENABLE}}
\DoxyCodeLine{03059\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03060\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03061\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM1\_FORCE\_RESET}}
\DoxyCodeLine{03062\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM1\_RELEASE\_RESET}}
\DoxyCodeLine{03063\ \textcolor{preprocessor}{\#define\ \_\_TIM10\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM10\_CLK\_DISABLE}}
\DoxyCodeLine{03064\ \textcolor{preprocessor}{\#define\ \_\_TIM10\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM10\_CLK\_ENABLE}}
\DoxyCodeLine{03065\ \textcolor{preprocessor}{\#define\ \_\_TIM10\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM10\_FORCE\_RESET}}
\DoxyCodeLine{03066\ \textcolor{preprocessor}{\#define\ \_\_TIM10\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM10\_RELEASE\_RESET}}
\DoxyCodeLine{03067\ \textcolor{preprocessor}{\#define\ \_\_TIM11\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM11\_CLK\_DISABLE}}
\DoxyCodeLine{03068\ \textcolor{preprocessor}{\#define\ \_\_TIM11\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM11\_CLK\_ENABLE}}
\DoxyCodeLine{03069\ \textcolor{preprocessor}{\#define\ \_\_TIM11\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM11\_FORCE\_RESET}}
\DoxyCodeLine{03070\ \textcolor{preprocessor}{\#define\ \_\_TIM11\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM11\_RELEASE\_RESET}}
\DoxyCodeLine{03071\ \textcolor{preprocessor}{\#define\ \_\_TIM12\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM12\_CLK\_DISABLE}}
\DoxyCodeLine{03072\ \textcolor{preprocessor}{\#define\ \_\_TIM12\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM12\_CLK\_ENABLE}}
\DoxyCodeLine{03073\ \textcolor{preprocessor}{\#define\ \_\_TIM12\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM12\_FORCE\_RESET}}
\DoxyCodeLine{03074\ \textcolor{preprocessor}{\#define\ \_\_TIM12\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM12\_RELEASE\_RESET}}
\DoxyCodeLine{03075\ \textcolor{preprocessor}{\#define\ \_\_TIM13\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM13\_CLK\_DISABLE}}
\DoxyCodeLine{03076\ \textcolor{preprocessor}{\#define\ \_\_TIM13\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM13\_CLK\_ENABLE}}
\DoxyCodeLine{03077\ \textcolor{preprocessor}{\#define\ \_\_TIM13\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM13\_FORCE\_RESET}}
\DoxyCodeLine{03078\ \textcolor{preprocessor}{\#define\ \_\_TIM13\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM13\_RELEASE\_RESET}}
\DoxyCodeLine{03079\ \textcolor{preprocessor}{\#define\ \_\_TIM14\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM14\_CLK\_DISABLE}}
\DoxyCodeLine{03080\ \textcolor{preprocessor}{\#define\ \_\_TIM14\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM14\_CLK\_ENABLE}}
\DoxyCodeLine{03081\ \textcolor{preprocessor}{\#define\ \_\_TIM14\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM14\_FORCE\_RESET}}
\DoxyCodeLine{03082\ \textcolor{preprocessor}{\#define\ \_\_TIM14\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM14\_RELEASE\_RESET}}
\DoxyCodeLine{03083\ \textcolor{preprocessor}{\#define\ \_\_TIM15\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM15\_CLK\_DISABLE}}
\DoxyCodeLine{03084\ \textcolor{preprocessor}{\#define\ \_\_TIM15\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM15\_CLK\_ENABLE}}
\DoxyCodeLine{03085\ \textcolor{preprocessor}{\#define\ \_\_TIM15\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM15\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03086\ \textcolor{preprocessor}{\#define\ \_\_TIM15\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM15\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03087\ \textcolor{preprocessor}{\#define\ \_\_TIM15\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM15\_FORCE\_RESET}}
\DoxyCodeLine{03088\ \textcolor{preprocessor}{\#define\ \_\_TIM15\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM15\_RELEASE\_RESET}}
\DoxyCodeLine{03089\ \textcolor{preprocessor}{\#define\ \_\_TIM16\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM16\_CLK\_DISABLE}}
\DoxyCodeLine{03090\ \textcolor{preprocessor}{\#define\ \_\_TIM16\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM16\_CLK\_ENABLE}}
\DoxyCodeLine{03091\ \textcolor{preprocessor}{\#define\ \_\_TIM16\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM16\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03092\ \textcolor{preprocessor}{\#define\ \_\_TIM16\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM16\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03093\ \textcolor{preprocessor}{\#define\ \_\_TIM16\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM16\_FORCE\_RESET}}
\DoxyCodeLine{03094\ \textcolor{preprocessor}{\#define\ \_\_TIM16\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM16\_RELEASE\_RESET}}
\DoxyCodeLine{03095\ \textcolor{preprocessor}{\#define\ \_\_TIM17\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM17\_CLK\_DISABLE}}
\DoxyCodeLine{03096\ \textcolor{preprocessor}{\#define\ \_\_TIM17\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM17\_CLK\_ENABLE}}
\DoxyCodeLine{03097\ \textcolor{preprocessor}{\#define\ \_\_TIM17\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM17\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03098\ \textcolor{preprocessor}{\#define\ \_\_TIM17\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM17\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03099\ \textcolor{preprocessor}{\#define\ \_\_TIM17\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM17\_FORCE\_RESET}}
\DoxyCodeLine{03100\ \textcolor{preprocessor}{\#define\ \_\_TIM17\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM17\_RELEASE\_RESET}}
\DoxyCodeLine{03101\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM2\_CLK\_DISABLE}}
\DoxyCodeLine{03102\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM2\_CLK\_ENABLE}}
\DoxyCodeLine{03103\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03104\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03105\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM2\_FORCE\_RESET}}
\DoxyCodeLine{03106\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM2\_RELEASE\_RESET}}
\DoxyCodeLine{03107\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM3\_CLK\_DISABLE}}
\DoxyCodeLine{03108\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM3\_CLK\_ENABLE}}
\DoxyCodeLine{03109\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM3\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03110\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM3\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03111\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM3\_FORCE\_RESET}}
\DoxyCodeLine{03112\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM3\_RELEASE\_RESET}}
\DoxyCodeLine{03113\ \textcolor{preprocessor}{\#define\ \_\_TIM4\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM4\_CLK\_DISABLE}}
\DoxyCodeLine{03114\ \textcolor{preprocessor}{\#define\ \_\_TIM4\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM4\_CLK\_ENABLE}}
\DoxyCodeLine{03115\ \textcolor{preprocessor}{\#define\ \_\_TIM4\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM4\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03116\ \textcolor{preprocessor}{\#define\ \_\_TIM4\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM4\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03117\ \textcolor{preprocessor}{\#define\ \_\_TIM4\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM4\_FORCE\_RESET}}
\DoxyCodeLine{03118\ \textcolor{preprocessor}{\#define\ \_\_TIM4\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM4\_RELEASE\_RESET}}
\DoxyCodeLine{03119\ \textcolor{preprocessor}{\#define\ \_\_TIM5\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM5\_CLK\_DISABLE}}
\DoxyCodeLine{03120\ \textcolor{preprocessor}{\#define\ \_\_TIM5\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM5\_CLK\_ENABLE}}
\DoxyCodeLine{03121\ \textcolor{preprocessor}{\#define\ \_\_TIM5\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM5\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03122\ \textcolor{preprocessor}{\#define\ \_\_TIM5\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM5\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03123\ \textcolor{preprocessor}{\#define\ \_\_TIM5\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM5\_FORCE\_RESET}}
\DoxyCodeLine{03124\ \textcolor{preprocessor}{\#define\ \_\_TIM5\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM5\_RELEASE\_RESET}}
\DoxyCodeLine{03125\ \textcolor{preprocessor}{\#define\ \_\_TIM6\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM6\_CLK\_DISABLE}}
\DoxyCodeLine{03126\ \textcolor{preprocessor}{\#define\ \_\_TIM6\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM6\_CLK\_ENABLE}}
\DoxyCodeLine{03127\ \textcolor{preprocessor}{\#define\ \_\_TIM6\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM6\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03128\ \textcolor{preprocessor}{\#define\ \_\_TIM6\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM6\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03129\ \textcolor{preprocessor}{\#define\ \_\_TIM6\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM6\_FORCE\_RESET}}
\DoxyCodeLine{03130\ \textcolor{preprocessor}{\#define\ \_\_TIM6\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM6\_RELEASE\_RESET}}
\DoxyCodeLine{03131\ \textcolor{preprocessor}{\#define\ \_\_TIM7\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM7\_CLK\_DISABLE}}
\DoxyCodeLine{03132\ \textcolor{preprocessor}{\#define\ \_\_TIM7\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM7\_CLK\_ENABLE}}
\DoxyCodeLine{03133\ \textcolor{preprocessor}{\#define\ \_\_TIM7\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM7\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03134\ \textcolor{preprocessor}{\#define\ \_\_TIM7\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM7\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03135\ \textcolor{preprocessor}{\#define\ \_\_TIM7\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM7\_FORCE\_RESET}}
\DoxyCodeLine{03136\ \textcolor{preprocessor}{\#define\ \_\_TIM7\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM7\_RELEASE\_RESET}}
\DoxyCodeLine{03137\ \textcolor{preprocessor}{\#define\ \_\_TIM8\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM8\_CLK\_DISABLE}}
\DoxyCodeLine{03138\ \textcolor{preprocessor}{\#define\ \_\_TIM8\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM8\_CLK\_ENABLE}}
\DoxyCodeLine{03139\ \textcolor{preprocessor}{\#define\ \_\_TIM8\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TIM8\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03140\ \textcolor{preprocessor}{\#define\ \_\_TIM8\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TIM8\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03141\ \textcolor{preprocessor}{\#define\ \_\_TIM8\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM8\_FORCE\_RESET}}
\DoxyCodeLine{03142\ \textcolor{preprocessor}{\#define\ \_\_TIM8\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM8\_RELEASE\_RESET}}
\DoxyCodeLine{03143\ \textcolor{preprocessor}{\#define\ \_\_TIM9\_CLK\_DISABLE\ \_\_HAL\_RCC\_TIM9\_CLK\_DISABLE}}
\DoxyCodeLine{03144\ \textcolor{preprocessor}{\#define\ \_\_TIM9\_CLK\_ENABLE\ \_\_HAL\_RCC\_TIM9\_CLK\_ENABLE}}
\DoxyCodeLine{03145\ \textcolor{preprocessor}{\#define\ \_\_TIM9\_FORCE\_RESET\ \_\_HAL\_RCC\_TIM9\_FORCE\_RESET}}
\DoxyCodeLine{03146\ \textcolor{preprocessor}{\#define\ \_\_TIM9\_RELEASE\_RESET\ \_\_HAL\_RCC\_TIM9\_RELEASE\_RESET}}
\DoxyCodeLine{03147\ \textcolor{preprocessor}{\#define\ \_\_TSC\_CLK\_DISABLE\ \_\_HAL\_RCC\_TSC\_CLK\_DISABLE}}
\DoxyCodeLine{03148\ \textcolor{preprocessor}{\#define\ \_\_TSC\_CLK\_ENABLE\ \_\_HAL\_RCC\_TSC\_CLK\_ENABLE}}
\DoxyCodeLine{03149\ \textcolor{preprocessor}{\#define\ \_\_TSC\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_TSC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03150\ \textcolor{preprocessor}{\#define\ \_\_TSC\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_TSC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03151\ \textcolor{preprocessor}{\#define\ \_\_TSC\_FORCE\_RESET\ \_\_HAL\_RCC\_TSC\_FORCE\_RESET}}
\DoxyCodeLine{03152\ \textcolor{preprocessor}{\#define\ \_\_TSC\_RELEASE\_RESET\ \_\_HAL\_RCC\_TSC\_RELEASE\_RESET}}
\DoxyCodeLine{03153\ \textcolor{preprocessor}{\#define\ \_\_UART4\_CLK\_DISABLE\ \_\_HAL\_RCC\_UART4\_CLK\_DISABLE}}
\DoxyCodeLine{03154\ \textcolor{preprocessor}{\#define\ \_\_UART4\_CLK\_ENABLE\ \_\_HAL\_RCC\_UART4\_CLK\_ENABLE}}
\DoxyCodeLine{03155\ \textcolor{preprocessor}{\#define\ \_\_UART4\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_UART4\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03156\ \textcolor{preprocessor}{\#define\ \_\_UART4\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_UART4\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03157\ \textcolor{preprocessor}{\#define\ \_\_UART4\_FORCE\_RESET\ \_\_HAL\_RCC\_UART4\_FORCE\_RESET}}
\DoxyCodeLine{03158\ \textcolor{preprocessor}{\#define\ \_\_UART4\_RELEASE\_RESET\ \_\_HAL\_RCC\_UART4\_RELEASE\_RESET}}
\DoxyCodeLine{03159\ \textcolor{preprocessor}{\#define\ \_\_UART5\_CLK\_DISABLE\ \_\_HAL\_RCC\_UART5\_CLK\_DISABLE}}
\DoxyCodeLine{03160\ \textcolor{preprocessor}{\#define\ \_\_UART5\_CLK\_ENABLE\ \_\_HAL\_RCC\_UART5\_CLK\_ENABLE}}
\DoxyCodeLine{03161\ \textcolor{preprocessor}{\#define\ \_\_UART5\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_UART5\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03162\ \textcolor{preprocessor}{\#define\ \_\_UART5\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_UART5\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03163\ \textcolor{preprocessor}{\#define\ \_\_UART5\_FORCE\_RESET\ \_\_HAL\_RCC\_UART5\_FORCE\_RESET}}
\DoxyCodeLine{03164\ \textcolor{preprocessor}{\#define\ \_\_UART5\_RELEASE\_RESET\ \_\_HAL\_RCC\_UART5\_RELEASE\_RESET}}
\DoxyCodeLine{03165\ \textcolor{preprocessor}{\#define\ \_\_USART1\_CLK\_DISABLE\ \_\_HAL\_RCC\_USART1\_CLK\_DISABLE}}
\DoxyCodeLine{03166\ \textcolor{preprocessor}{\#define\ \_\_USART1\_CLK\_ENABLE\ \_\_HAL\_RCC\_USART1\_CLK\_ENABLE}}
\DoxyCodeLine{03167\ \textcolor{preprocessor}{\#define\ \_\_USART1\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_USART1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03168\ \textcolor{preprocessor}{\#define\ \_\_USART1\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_USART1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03169\ \textcolor{preprocessor}{\#define\ \_\_USART1\_FORCE\_RESET\ \_\_HAL\_RCC\_USART1\_FORCE\_RESET}}
\DoxyCodeLine{03170\ \textcolor{preprocessor}{\#define\ \_\_USART1\_RELEASE\_RESET\ \_\_HAL\_RCC\_USART1\_RELEASE\_RESET}}
\DoxyCodeLine{03171\ \textcolor{preprocessor}{\#define\ \_\_USART2\_CLK\_DISABLE\ \_\_HAL\_RCC\_USART2\_CLK\_DISABLE}}
\DoxyCodeLine{03172\ \textcolor{preprocessor}{\#define\ \_\_USART2\_CLK\_ENABLE\ \_\_HAL\_RCC\_USART2\_CLK\_ENABLE}}
\DoxyCodeLine{03173\ \textcolor{preprocessor}{\#define\ \_\_USART2\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_USART2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03174\ \textcolor{preprocessor}{\#define\ \_\_USART2\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_USART2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03175\ \textcolor{preprocessor}{\#define\ \_\_USART2\_FORCE\_RESET\ \_\_HAL\_RCC\_USART2\_FORCE\_RESET}}
\DoxyCodeLine{03176\ \textcolor{preprocessor}{\#define\ \_\_USART2\_RELEASE\_RESET\ \_\_HAL\_RCC\_USART2\_RELEASE\_RESET}}
\DoxyCodeLine{03177\ \textcolor{preprocessor}{\#define\ \_\_USART3\_CLK\_DISABLE\ \_\_HAL\_RCC\_USART3\_CLK\_DISABLE}}
\DoxyCodeLine{03178\ \textcolor{preprocessor}{\#define\ \_\_USART3\_CLK\_ENABLE\ \_\_HAL\_RCC\_USART3\_CLK\_ENABLE}}
\DoxyCodeLine{03179\ \textcolor{preprocessor}{\#define\ \_\_USART3\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_USART3\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03180\ \textcolor{preprocessor}{\#define\ \_\_USART3\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_USART3\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03181\ \textcolor{preprocessor}{\#define\ \_\_USART3\_FORCE\_RESET\ \_\_HAL\_RCC\_USART3\_FORCE\_RESET}}
\DoxyCodeLine{03182\ \textcolor{preprocessor}{\#define\ \_\_USART3\_RELEASE\_RESET\ \_\_HAL\_RCC\_USART3\_RELEASE\_RESET}}
\DoxyCodeLine{03183\ \textcolor{preprocessor}{\#define\ \_\_USART4\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART4\_CLK\_DISABLE}}
\DoxyCodeLine{03184\ \textcolor{preprocessor}{\#define\ \_\_USART4\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART4\_CLK\_ENABLE}}
\DoxyCodeLine{03185\ \textcolor{preprocessor}{\#define\ \_\_USART4\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_UART4\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03186\ \textcolor{preprocessor}{\#define\ \_\_USART4\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_UART4\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03187\ \textcolor{preprocessor}{\#define\ \_\_USART4\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART4\_FORCE\_RESET}}
\DoxyCodeLine{03188\ \textcolor{preprocessor}{\#define\ \_\_USART4\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_UART4\_RELEASE\_RESET}}
\DoxyCodeLine{03189\ \textcolor{preprocessor}{\#define\ \_\_USART5\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART5\_CLK\_DISABLE}}
\DoxyCodeLine{03190\ \textcolor{preprocessor}{\#define\ \_\_USART5\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART5\_CLK\_ENABLE}}
\DoxyCodeLine{03191\ \textcolor{preprocessor}{\#define\ \_\_USART5\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_UART5\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03192\ \textcolor{preprocessor}{\#define\ \_\_USART5\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_UART5\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03193\ \textcolor{preprocessor}{\#define\ \_\_USART5\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART5\_FORCE\_RESET}}
\DoxyCodeLine{03194\ \textcolor{preprocessor}{\#define\ \_\_USART5\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_UART5\_RELEASE\_RESET}}
\DoxyCodeLine{03195\ \textcolor{preprocessor}{\#define\ \_\_USART7\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_CLK\_DISABLE}}
\DoxyCodeLine{03196\ \textcolor{preprocessor}{\#define\ \_\_USART7\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_CLK\_ENABLE}}
\DoxyCodeLine{03197\ \textcolor{preprocessor}{\#define\ \_\_USART7\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_FORCE\_RESET}}
\DoxyCodeLine{03198\ \textcolor{preprocessor}{\#define\ \_\_USART7\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_RELEASE\_RESET}}
\DoxyCodeLine{03199\ \textcolor{preprocessor}{\#define\ \_\_USART8\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_CLK\_DISABLE}}
\DoxyCodeLine{03200\ \textcolor{preprocessor}{\#define\ \_\_USART8\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_CLK\_ENABLE}}
\DoxyCodeLine{03201\ \textcolor{preprocessor}{\#define\ \_\_USART8\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_FORCE\_RESET}}
\DoxyCodeLine{03202\ \textcolor{preprocessor}{\#define\ \_\_USART8\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_RELEASE\_RESET}}
\DoxyCodeLine{03203\ \textcolor{preprocessor}{\#define\ \_\_USB\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_CLK\_DISABLE}}
\DoxyCodeLine{03204\ \textcolor{preprocessor}{\#define\ \_\_USB\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_CLK\_ENABLE}}
\DoxyCodeLine{03205\ \textcolor{preprocessor}{\#define\ \_\_USB\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_FORCE\_RESET}}
\DoxyCodeLine{03206\ \textcolor{preprocessor}{\#define\ \_\_USB\_CLK\_SLEEP\_ENABLE\ \ \ \ \_\_HAL\_RCC\_USB\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03207\ \textcolor{preprocessor}{\#define\ \_\_USB\_CLK\_SLEEP\_DISABLE\ \ \ \_\_HAL\_RCC\_USB\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03208\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_FS\_CLK\_DISABLE\ \_\_HAL\_RCC\_USB\_OTG\_FS\_CLK\_DISABLE}}
\DoxyCodeLine{03209\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_FS\_CLK\_ENABLE\ \_\_HAL\_RCC\_USB\_OTG\_FS\_CLK\_ENABLE}}
\DoxyCodeLine{03210\ \textcolor{preprocessor}{\#define\ \_\_USB\_RELEASE\_RESET\ \_\_HAL\_RCC\_USB\_RELEASE\_RESET}}
\DoxyCodeLine{03211\ }
\DoxyCodeLine{03212\ \textcolor{preprocessor}{\#if\ defined(STM32H7)}}
\DoxyCodeLine{03213\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG\_CLK\_DISABLE\ \ \ \_\_HAL\_RCC\_WWDG1\_CLK\_DISABLE}}
\DoxyCodeLine{03214\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG\_CLK\_ENABLE\ \ \ \_\_HAL\_RCC\_WWDG1\_CLK\_ENABLE}}
\DoxyCodeLine{03215\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_WWDG1\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03216\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_WWDG1\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03217\ }
\DoxyCodeLine{03218\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG\_FORCE\_RESET\ \ \ \ ((void)0U)\ \ }\textcolor{comment}{/*\ Not\ available\ on\ the\ STM32H7*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{03219\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_WWDG\_RELEASE\_RESET\ ((void)0U)\ }\textcolor{comment}{/*\ Not\ available\ on\ the\ STM32H7*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{03220\ }
\DoxyCodeLine{03221\ }
\DoxyCodeLine{03222\ \textcolor{preprocessor}{\#define\ \ \_\_HAL\_RCC\_WWDG\_IS\_CLK\_ENABLED\ \ \ \ \_\_HAL\_RCC\_WWDG1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03223\ \textcolor{preprocessor}{\#define\ \ \_\_HAL\_RCC\_WWDG\_IS\_CLK\_DISABLED\ \ \_\_HAL\_RCC\_WWDG1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03224\ \textcolor{preprocessor}{\#define\ \ RCC\_SPI4CLKSOURCE\_D2PCLK1\ \ \ \ \ \ \ RCC\_SPI4CLKSOURCE\_D2PCLK2}}
\DoxyCodeLine{03225\ \textcolor{preprocessor}{\#define\ \ RCC\_SPI5CLKSOURCE\_D2PCLK1\ \ \ \ \ \ \ RCC\_SPI5CLKSOURCE\_D2PCLK2}}
\DoxyCodeLine{03226\ \textcolor{preprocessor}{\#define\ \ RCC\_SPI45CLKSOURCE\_D2PCLK1\ \ \ \ \ \ RCC\_SPI45CLKSOURCE\_D2PCLK2}}
\DoxyCodeLine{03227\ \textcolor{preprocessor}{\#define\ \ RCC\_SPI45CLKSOURCE\_CDPCLK1\ \ \ \ \ \ RCC\_SPI45CLKSOURCE\_CDPCLK2}}
\DoxyCodeLine{03228\ \textcolor{preprocessor}{\#define\ \ RCC\_SPI45CLKSOURCE\_PCLK1\ \ \ \ \ \ \ \ RCC\_SPI45CLKSOURCE\_PCLK2}}
\DoxyCodeLine{03229\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{03230\ }
\DoxyCodeLine{03231\ \textcolor{preprocessor}{\#define\ \_\_WWDG\_CLK\_DISABLE\ \_\_HAL\_RCC\_WWDG\_CLK\_DISABLE}}
\DoxyCodeLine{03232\ \textcolor{preprocessor}{\#define\ \_\_WWDG\_CLK\_ENABLE\ \_\_HAL\_RCC\_WWDG\_CLK\_ENABLE}}
\DoxyCodeLine{03233\ \textcolor{preprocessor}{\#define\ \_\_WWDG\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_WWDG\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03234\ \textcolor{preprocessor}{\#define\ \_\_WWDG\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_WWDG\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03235\ \textcolor{preprocessor}{\#define\ \_\_WWDG\_FORCE\_RESET\ \_\_HAL\_RCC\_WWDG\_FORCE\_RESET}}
\DoxyCodeLine{03236\ \textcolor{preprocessor}{\#define\ \_\_WWDG\_RELEASE\_RESET\ \_\_HAL\_RCC\_WWDG\_RELEASE\_RESET}}
\DoxyCodeLine{03237\ }
\DoxyCodeLine{03238\ \textcolor{preprocessor}{\#define\ \_\_TIM21\_CLK\_ENABLE\ \ \ \_\_HAL\_RCC\_TIM21\_CLK\_ENABLE}}
\DoxyCodeLine{03239\ \textcolor{preprocessor}{\#define\ \_\_TIM21\_CLK\_DISABLE\ \ \ \_\_HAL\_RCC\_TIM21\_CLK\_DISABLE}}
\DoxyCodeLine{03240\ \textcolor{preprocessor}{\#define\ \_\_TIM21\_FORCE\_RESET\ \ \ \_\_HAL\_RCC\_TIM21\_FORCE\_RESET}}
\DoxyCodeLine{03241\ \textcolor{preprocessor}{\#define\ \_\_TIM21\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_TIM21\_RELEASE\_RESET}}
\DoxyCodeLine{03242\ \textcolor{preprocessor}{\#define\ \_\_TIM21\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_TIM21\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03243\ \textcolor{preprocessor}{\#define\ \_\_TIM21\_CLK\_SLEEP\_DISABLE\ \ \ \_\_HAL\_RCC\_TIM21\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03244\ \textcolor{preprocessor}{\#define\ \_\_TIM22\_CLK\_ENABLE\ \ \ \_\_HAL\_RCC\_TIM22\_CLK\_ENABLE}}
\DoxyCodeLine{03245\ \textcolor{preprocessor}{\#define\ \_\_TIM22\_CLK\_DISABLE\ \ \ \_\_HAL\_RCC\_TIM22\_CLK\_DISABLE}}
\DoxyCodeLine{03246\ \textcolor{preprocessor}{\#define\ \_\_TIM22\_FORCE\_RESET\ \ \ \_\_HAL\_RCC\_TIM22\_FORCE\_RESET}}
\DoxyCodeLine{03247\ \textcolor{preprocessor}{\#define\ \_\_TIM22\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_TIM22\_RELEASE\_RESET}}
\DoxyCodeLine{03248\ \textcolor{preprocessor}{\#define\ \_\_TIM22\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_TIM22\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03249\ \textcolor{preprocessor}{\#define\ \_\_TIM22\_CLK\_SLEEP\_DISABLE\ \ \ \_\_HAL\_RCC\_TIM22\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03250\ \textcolor{preprocessor}{\#define\ \_\_CRS\_CLK\_DISABLE\ \_\_HAL\_RCC\_CRS\_CLK\_DISABLE}}
\DoxyCodeLine{03251\ \textcolor{preprocessor}{\#define\ \_\_CRS\_CLK\_ENABLE\ \_\_HAL\_RCC\_CRS\_CLK\_ENABLE}}
\DoxyCodeLine{03252\ \textcolor{preprocessor}{\#define\ \_\_CRS\_CLK\_SLEEP\_DISABLE\ \_\_HAL\_RCC\_CRS\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03253\ \textcolor{preprocessor}{\#define\ \_\_CRS\_CLK\_SLEEP\_ENABLE\ \_\_HAL\_RCC\_CRS\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03254\ \textcolor{preprocessor}{\#define\ \_\_CRS\_FORCE\_RESET\ \_\_HAL\_RCC\_CRS\_FORCE\_RESET}}
\DoxyCodeLine{03255\ \textcolor{preprocessor}{\#define\ \_\_CRS\_RELEASE\_RESET\ \_\_HAL\_RCC\_CRS\_RELEASE\_RESET}}
\DoxyCodeLine{03256\ \textcolor{preprocessor}{\#define\ \_\_RCC\_BACKUPRESET\_FORCE\ \_\_HAL\_RCC\_BACKUPRESET\_FORCE}}
\DoxyCodeLine{03257\ \textcolor{preprocessor}{\#define\ \_\_RCC\_BACKUPRESET\_RELEASE\ \_\_HAL\_RCC\_BACKUPRESET\_RELEASE}}
\DoxyCodeLine{03258\ }
\DoxyCodeLine{03259\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_FS\_FORCE\_RESET\ \ \_\_HAL\_RCC\_USB\_OTG\_FS\_FORCE\_RESET}}
\DoxyCodeLine{03260\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_FS\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_USB\_OTG\_FS\_RELEASE\_RESET}}
\DoxyCodeLine{03261\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_FS\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_FS\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03262\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_FS\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_FS\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03263\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_HS\_CLK\_DISABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_CLK\_DISABLE}}
\DoxyCodeLine{03264\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_HS\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_CLK\_ENABLE}}
\DoxyCodeLine{03265\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_HS\_ULPI\_CLK\_ENABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_CLK\_ENABLE}}
\DoxyCodeLine{03266\ \textcolor{preprocessor}{\#define\ \_\_USB\_OTG\_HS\_ULPI\_CLK\_DISABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_CLK\_DISABLE}}
\DoxyCodeLine{03267\ \textcolor{preprocessor}{\#define\ \_\_TIM9\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM9\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03268\ \textcolor{preprocessor}{\#define\ \_\_TIM9\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_TIM9\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03269\ \textcolor{preprocessor}{\#define\ \_\_TIM10\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_TIM10\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03270\ \textcolor{preprocessor}{\#define\ \_\_TIM10\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_TIM10\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03271\ \textcolor{preprocessor}{\#define\ \_\_TIM11\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_TIM11\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03272\ \textcolor{preprocessor}{\#define\ \_\_TIM11\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_TIM11\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03273\ \textcolor{preprocessor}{\#define\ \_\_ETHMACPTP\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_ETHMACPTP\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03274\ \textcolor{preprocessor}{\#define\ \_\_ETHMACPTP\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_ETHMACPTP\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03275\ \textcolor{preprocessor}{\#define\ \_\_ETHMACPTP\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ETHMACPTP\_CLK\_ENABLE}}
\DoxyCodeLine{03276\ \textcolor{preprocessor}{\#define\ \_\_ETHMACPTP\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ETHMACPTP\_CLK\_DISABLE}}
\DoxyCodeLine{03277\ \textcolor{preprocessor}{\#define\ \_\_HASH\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HASH\_CLK\_ENABLE}}
\DoxyCodeLine{03278\ \textcolor{preprocessor}{\#define\ \_\_HASH\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HASH\_FORCE\_RESET}}
\DoxyCodeLine{03279\ \textcolor{preprocessor}{\#define\ \_\_HASH\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HASH\_RELEASE\_RESET}}
\DoxyCodeLine{03280\ \textcolor{preprocessor}{\#define\ \_\_HASH\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HASH\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03281\ \textcolor{preprocessor}{\#define\ \_\_HASH\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_HASH\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03282\ \textcolor{preprocessor}{\#define\ \_\_HASH\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HASH\_CLK\_DISABLE}}
\DoxyCodeLine{03283\ \textcolor{preprocessor}{\#define\ \_\_SPI5\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI5\_CLK\_ENABLE}}
\DoxyCodeLine{03284\ \textcolor{preprocessor}{\#define\ \_\_SPI5\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI5\_CLK\_DISABLE}}
\DoxyCodeLine{03285\ \textcolor{preprocessor}{\#define\ \_\_SPI5\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI5\_FORCE\_RESET}}
\DoxyCodeLine{03286\ \textcolor{preprocessor}{\#define\ \_\_SPI5\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI5\_RELEASE\_RESET}}
\DoxyCodeLine{03287\ \textcolor{preprocessor}{\#define\ \_\_SPI5\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI5\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03288\ \textcolor{preprocessor}{\#define\ \_\_SPI5\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_SPI5\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03289\ \textcolor{preprocessor}{\#define\ \_\_SPI6\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI6\_CLK\_ENABLE}}
\DoxyCodeLine{03290\ \textcolor{preprocessor}{\#define\ \_\_SPI6\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI6\_CLK\_DISABLE}}
\DoxyCodeLine{03291\ \textcolor{preprocessor}{\#define\ \_\_SPI6\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI6\_FORCE\_RESET}}
\DoxyCodeLine{03292\ \textcolor{preprocessor}{\#define\ \_\_SPI6\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI6\_RELEASE\_RESET}}
\DoxyCodeLine{03293\ \textcolor{preprocessor}{\#define\ \_\_SPI6\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI6\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03294\ \textcolor{preprocessor}{\#define\ \_\_SPI6\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_SPI6\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03295\ \textcolor{preprocessor}{\#define\ \_\_LTDC\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_LTDC\_CLK\_ENABLE}}
\DoxyCodeLine{03296\ \textcolor{preprocessor}{\#define\ \_\_LTDC\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_LTDC\_CLK\_DISABLE}}
\DoxyCodeLine{03297\ \textcolor{preprocessor}{\#define\ \_\_LTDC\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_LTDC\_FORCE\_RESET}}
\DoxyCodeLine{03298\ \textcolor{preprocessor}{\#define\ \_\_LTDC\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_LTDC\_RELEASE\_RESET}}
\DoxyCodeLine{03299\ \textcolor{preprocessor}{\#define\ \_\_LTDC\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_LTDC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03300\ \textcolor{preprocessor}{\#define\ \_\_ETHMAC\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_ETHMAC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03301\ \textcolor{preprocessor}{\#define\ \_\_ETHMAC\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_ETHMAC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03302\ \textcolor{preprocessor}{\#define\ \_\_ETHMACTX\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_ETHMACTX\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03303\ \textcolor{preprocessor}{\#define\ \_\_ETHMACTX\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_ETHMACTX\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03304\ \textcolor{preprocessor}{\#define\ \_\_ETHMACRX\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_ETHMACRX\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03305\ \textcolor{preprocessor}{\#define\ \_\_ETHMACRX\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_ETHMACRX\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03306\ \textcolor{preprocessor}{\#define\ \_\_TIM12\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_TIM12\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03307\ \textcolor{preprocessor}{\#define\ \_\_TIM12\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_TIM12\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03308\ \textcolor{preprocessor}{\#define\ \_\_TIM13\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_TIM13\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03309\ \textcolor{preprocessor}{\#define\ \_\_TIM13\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_TIM13\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03310\ \textcolor{preprocessor}{\#define\ \_\_TIM14\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_TIM14\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03311\ \textcolor{preprocessor}{\#define\ \_\_TIM14\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_TIM14\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03312\ \textcolor{preprocessor}{\#define\ \_\_BKPSRAM\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_BKPSRAM\_CLK\_ENABLE}}
\DoxyCodeLine{03313\ \textcolor{preprocessor}{\#define\ \_\_BKPSRAM\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_BKPSRAM\_CLK\_DISABLE}}
\DoxyCodeLine{03314\ \textcolor{preprocessor}{\#define\ \_\_BKPSRAM\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_BKPSRAM\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03315\ \textcolor{preprocessor}{\#define\ \_\_BKPSRAM\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_BKPSRAM\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03316\ \textcolor{preprocessor}{\#define\ \_\_CCMDATARAMEN\_CLK\_ENABLE\ \ \_\_HAL\_RCC\_CCMDATARAMEN\_CLK\_ENABLE}}
\DoxyCodeLine{03317\ \textcolor{preprocessor}{\#define\ \_\_CCMDATARAMEN\_CLK\_DISABLE\ \ \_\_HAL\_RCC\_CCMDATARAMEN\_CLK\_DISABLE}}
\DoxyCodeLine{03318\ \textcolor{preprocessor}{\#define\ \_\_USART6\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USART6\_CLK\_ENABLE}}
\DoxyCodeLine{03319\ \textcolor{preprocessor}{\#define\ \_\_USART6\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USART6\_CLK\_DISABLE}}
\DoxyCodeLine{03320\ \textcolor{preprocessor}{\#define\ \_\_USART6\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USART6\_FORCE\_RESET}}
\DoxyCodeLine{03321\ \textcolor{preprocessor}{\#define\ \_\_USART6\_RELEASE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USART6\_RELEASE\_RESET}}
\DoxyCodeLine{03322\ \textcolor{preprocessor}{\#define\ \_\_USART6\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_USART6\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03323\ \textcolor{preprocessor}{\#define\ \_\_USART6\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_USART6\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03324\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI4\_CLK\_ENABLE}}
\DoxyCodeLine{03325\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI4\_CLK\_DISABLE}}
\DoxyCodeLine{03326\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI4\_FORCE\_RESET}}
\DoxyCodeLine{03327\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_RELEASE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI4\_RELEASE\_RESET}}
\DoxyCodeLine{03328\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_SPI4\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03329\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_SPI4\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03330\ \textcolor{preprocessor}{\#define\ \_\_GPIOI\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOI\_CLK\_ENABLE}}
\DoxyCodeLine{03331\ \textcolor{preprocessor}{\#define\ \_\_GPIOI\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOI\_CLK\_DISABLE}}
\DoxyCodeLine{03332\ \textcolor{preprocessor}{\#define\ \_\_GPIOI\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOI\_FORCE\_RESET}}
\DoxyCodeLine{03333\ \textcolor{preprocessor}{\#define\ \_\_GPIOI\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOI\_RELEASE\_RESET}}
\DoxyCodeLine{03334\ \textcolor{preprocessor}{\#define\ \_\_GPIOI\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_GPIOI\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03335\ \textcolor{preprocessor}{\#define\ \_\_GPIOI\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_GPIOI\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03336\ \textcolor{preprocessor}{\#define\ \_\_GPIOJ\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOJ\_CLK\_ENABLE}}
\DoxyCodeLine{03337\ \textcolor{preprocessor}{\#define\ \_\_GPIOJ\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOJ\_CLK\_DISABLE}}
\DoxyCodeLine{03338\ \textcolor{preprocessor}{\#define\ \_\_GPIOJ\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOJ\_FORCE\_RESET}}
\DoxyCodeLine{03339\ \textcolor{preprocessor}{\#define\ \_\_GPIOJ\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOJ\_RELEASE\_RESET}}
\DoxyCodeLine{03340\ \textcolor{preprocessor}{\#define\ \_\_GPIOJ\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_GPIOJ\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03341\ \textcolor{preprocessor}{\#define\ \_\_GPIOJ\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_GPIOJ\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03342\ \textcolor{preprocessor}{\#define\ \_\_GPIOK\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOK\_CLK\_ENABLE}}
\DoxyCodeLine{03343\ \textcolor{preprocessor}{\#define\ \_\_GPIOK\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOK\_CLK\_DISABLE}}
\DoxyCodeLine{03344\ \textcolor{preprocessor}{\#define\ \_\_GPIOK\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_GPIOK\_RELEASE\_RESET}}
\DoxyCodeLine{03345\ \textcolor{preprocessor}{\#define\ \_\_GPIOK\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_GPIOK\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03346\ \textcolor{preprocessor}{\#define\ \_\_GPIOK\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_GPIOK\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03347\ \textcolor{preprocessor}{\#define\ \_\_ETH\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ETH\_CLK\_ENABLE}}
\DoxyCodeLine{03348\ \textcolor{preprocessor}{\#define\ \_\_ETH\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ETH\_CLK\_DISABLE}}
\DoxyCodeLine{03349\ \textcolor{preprocessor}{\#define\ \_\_DCMI\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DCMI\_CLK\_ENABLE}}
\DoxyCodeLine{03350\ \textcolor{preprocessor}{\#define\ \_\_DCMI\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DCMI\_CLK\_DISABLE}}
\DoxyCodeLine{03351\ \textcolor{preprocessor}{\#define\ \_\_DCMI\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DCMI\_FORCE\_RESET}}
\DoxyCodeLine{03352\ \textcolor{preprocessor}{\#define\ \_\_DCMI\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DCMI\_RELEASE\_RESET}}
\DoxyCodeLine{03353\ \textcolor{preprocessor}{\#define\ \_\_DCMI\_CLK\_SLEEP\_ENABLE\ \ \ \_\_HAL\_RCC\_DCMI\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03354\ \textcolor{preprocessor}{\#define\ \_\_DCMI\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_DCMI\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03355\ \textcolor{preprocessor}{\#define\ \_\_UART7\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_CLK\_ENABLE}}
\DoxyCodeLine{03356\ \textcolor{preprocessor}{\#define\ \_\_UART7\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_CLK\_DISABLE}}
\DoxyCodeLine{03357\ \textcolor{preprocessor}{\#define\ \_\_UART7\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_RELEASE\_RESET}}
\DoxyCodeLine{03358\ \textcolor{preprocessor}{\#define\ \_\_UART7\_FORCE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_UART7\_FORCE\_RESET}}
\DoxyCodeLine{03359\ \textcolor{preprocessor}{\#define\ \_\_UART7\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_UART7\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03360\ \textcolor{preprocessor}{\#define\ \_\_UART7\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_UART7\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03361\ \textcolor{preprocessor}{\#define\ \_\_UART8\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_CLK\_ENABLE}}
\DoxyCodeLine{03362\ \textcolor{preprocessor}{\#define\ \_\_UART8\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_CLK\_DISABLE}}
\DoxyCodeLine{03363\ \textcolor{preprocessor}{\#define\ \_\_UART8\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_FORCE\_RESET}}
\DoxyCodeLine{03364\ \textcolor{preprocessor}{\#define\ \_\_UART8\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_UART8\_RELEASE\_RESET}}
\DoxyCodeLine{03365\ \textcolor{preprocessor}{\#define\ \_\_UART8\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_UART8\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03366\ \textcolor{preprocessor}{\#define\ \_\_UART8\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_UART8\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03367\ \textcolor{preprocessor}{\#define\ \_\_OTGHS\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03368\ \textcolor{preprocessor}{\#define\ \_\_OTGHS\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03369\ \textcolor{preprocessor}{\#define\ \_\_OTGHS\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_FORCE\_RESET}}
\DoxyCodeLine{03370\ \textcolor{preprocessor}{\#define\ \_\_OTGHS\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_RELEASE\_RESET}}
\DoxyCodeLine{03371\ \textcolor{preprocessor}{\#define\ \_\_OTGHSULPI\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03372\ \textcolor{preprocessor}{\#define\ \_\_OTGHSULPI\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03373\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHS\_CLK\_SLEEP\_ENABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03374\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHS\_CLK\_SLEEP\_DISABLE\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03375\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHS\_IS\_CLK\_SLEEP\_ENABLED\ \_\_HAL\_RCC\_USB\_OTG\_HS\_IS\_CLK\_SLEEP\_ENABLED}}
\DoxyCodeLine{03376\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHS\_IS\_CLK\_SLEEP\_DISABLED\ \_\_HAL\_RCC\_USB\_OTG\_HS\_IS\_CLK\_SLEEP\_DISABLED}}
\DoxyCodeLine{03377\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHS\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_FORCE\_RESET}}
\DoxyCodeLine{03378\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHS\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_RELEASE\_RESET}}
\DoxyCodeLine{03379\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHSULPI\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03380\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHSULPI\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03381\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHSULPI\_IS\_CLK\_SLEEP\_ENABLED\ \ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_IS\_CLK\_SLEEP\_ENABLED}}
\DoxyCodeLine{03382\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGHSULPI\_IS\_CLK\_SLEEP\_DISABLED\ \_\_HAL\_RCC\_USB\_OTG\_HS\_ULPI\_IS\_CLK\_SLEEP\_DISABLED}}
\DoxyCodeLine{03383\ \textcolor{preprocessor}{\#define\ \_\_SRAM3\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_SRAM3\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03384\ \textcolor{preprocessor}{\#define\ \_\_CAN2\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_CAN2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03385\ \textcolor{preprocessor}{\#define\ \_\_CAN2\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_CAN2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03386\ \textcolor{preprocessor}{\#define\ \_\_DAC\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03387\ \textcolor{preprocessor}{\#define\ \_\_DAC\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03388\ \textcolor{preprocessor}{\#define\ \_\_ADC2\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC2\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03389\ \textcolor{preprocessor}{\#define\ \_\_ADC2\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC2\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03390\ \textcolor{preprocessor}{\#define\ \_\_ADC3\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC3\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03391\ \textcolor{preprocessor}{\#define\ \_\_ADC3\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC3\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03392\ \textcolor{preprocessor}{\#define\ \_\_FSMC\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_FSMC\_FORCE\_RESET}}
\DoxyCodeLine{03393\ \textcolor{preprocessor}{\#define\ \_\_FSMC\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_FSMC\_RELEASE\_RESET}}
\DoxyCodeLine{03394\ \textcolor{preprocessor}{\#define\ \_\_FSMC\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_FSMC\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03395\ \textcolor{preprocessor}{\#define\ \_\_FSMC\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_FSMC\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03396\ \textcolor{preprocessor}{\#define\ \_\_SDIO\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDIO\_FORCE\_RESET}}
\DoxyCodeLine{03397\ \textcolor{preprocessor}{\#define\ \_\_SDIO\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDIO\_RELEASE\_RESET}}
\DoxyCodeLine{03398\ \textcolor{preprocessor}{\#define\ \_\_SDIO\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_SDIO\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03399\ \textcolor{preprocessor}{\#define\ \_\_SDIO\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDIO\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03400\ \textcolor{preprocessor}{\#define\ \_\_DMA2D\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA2D\_CLK\_ENABLE}}
\DoxyCodeLine{03401\ \textcolor{preprocessor}{\#define\ \_\_DMA2D\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA2D\_CLK\_DISABLE}}
\DoxyCodeLine{03402\ \textcolor{preprocessor}{\#define\ \_\_DMA2D\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA2D\_FORCE\_RESET}}
\DoxyCodeLine{03403\ \textcolor{preprocessor}{\#define\ \_\_DMA2D\_RELEASE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA2D\_RELEASE\_RESET}}
\DoxyCodeLine{03404\ \textcolor{preprocessor}{\#define\ \_\_DMA2D\_CLK\_SLEEP\_ENABLE\ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA2D\_CLK\_SLEEP\_ENABLE}}
\DoxyCodeLine{03405\ \textcolor{preprocessor}{\#define\ \_\_DMA2D\_CLK\_SLEEP\_DISABLE\ \ \ \ \ \ \_\_HAL\_RCC\_DMA2D\_CLK\_SLEEP\_DISABLE}}
\DoxyCodeLine{03406\ }
\DoxyCodeLine{03407\ \textcolor{comment}{/*\ alias\ define\ maintained\ for\ legacy\ */}}
\DoxyCodeLine{03408\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGFS\_FORCE\_RESET\ \ \ \ \_\_HAL\_RCC\_USB\_OTG\_FS\_FORCE\_RESET}}
\DoxyCodeLine{03409\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_OTGFS\_RELEASE\_RESET\ \ \_\_HAL\_RCC\_USB\_OTG\_FS\_RELEASE\_RESET}}
\DoxyCodeLine{03410\ }
\DoxyCodeLine{03411\ \textcolor{preprocessor}{\#define\ \_\_ADC12\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC12\_CLK\_ENABLE}}
\DoxyCodeLine{03412\ \textcolor{preprocessor}{\#define\ \_\_ADC12\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC12\_CLK\_DISABLE}}
\DoxyCodeLine{03413\ \textcolor{preprocessor}{\#define\ \_\_ADC34\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC34\_CLK\_ENABLE}}
\DoxyCodeLine{03414\ \textcolor{preprocessor}{\#define\ \_\_ADC34\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC34\_CLK\_DISABLE}}
\DoxyCodeLine{03415\ \textcolor{preprocessor}{\#define\ \_\_DAC2\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC2\_CLK\_ENABLE}}
\DoxyCodeLine{03416\ \textcolor{preprocessor}{\#define\ \_\_DAC2\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC2\_CLK\_DISABLE}}
\DoxyCodeLine{03417\ \textcolor{preprocessor}{\#define\ \_\_TIM18\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM18\_CLK\_ENABLE}}
\DoxyCodeLine{03418\ \textcolor{preprocessor}{\#define\ \_\_TIM18\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM18\_CLK\_DISABLE}}
\DoxyCodeLine{03419\ \textcolor{preprocessor}{\#define\ \_\_TIM19\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM19\_CLK\_ENABLE}}
\DoxyCodeLine{03420\ \textcolor{preprocessor}{\#define\ \_\_TIM19\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM19\_CLK\_DISABLE}}
\DoxyCodeLine{03421\ \textcolor{preprocessor}{\#define\ \_\_TIM20\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM20\_CLK\_ENABLE}}
\DoxyCodeLine{03422\ \textcolor{preprocessor}{\#define\ \_\_TIM20\_CLK\_DISABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM20\_CLK\_DISABLE}}
\DoxyCodeLine{03423\ \textcolor{preprocessor}{\#define\ \_\_HRTIM1\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HRTIM1\_CLK\_ENABLE}}
\DoxyCodeLine{03424\ \textcolor{preprocessor}{\#define\ \_\_HRTIM1\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HRTIM1\_CLK\_DISABLE}}
\DoxyCodeLine{03425\ \textcolor{preprocessor}{\#define\ \_\_SDADC1\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC1\_CLK\_ENABLE}}
\DoxyCodeLine{03426\ \textcolor{preprocessor}{\#define\ \_\_SDADC2\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC2\_CLK\_ENABLE}}
\DoxyCodeLine{03427\ \textcolor{preprocessor}{\#define\ \_\_SDADC3\_CLK\_ENABLE\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC3\_CLK\_ENABLE}}
\DoxyCodeLine{03428\ \textcolor{preprocessor}{\#define\ \_\_SDADC1\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC1\_CLK\_DISABLE}}
\DoxyCodeLine{03429\ \textcolor{preprocessor}{\#define\ \_\_SDADC2\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC2\_CLK\_DISABLE}}
\DoxyCodeLine{03430\ \textcolor{preprocessor}{\#define\ \_\_SDADC3\_CLK\_DISABLE\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC3\_CLK\_DISABLE}}
\DoxyCodeLine{03431\ }
\DoxyCodeLine{03432\ \textcolor{preprocessor}{\#define\ \_\_ADC12\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC12\_FORCE\_RESET}}
\DoxyCodeLine{03433\ \textcolor{preprocessor}{\#define\ \_\_ADC12\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC12\_RELEASE\_RESET}}
\DoxyCodeLine{03434\ \textcolor{preprocessor}{\#define\ \_\_ADC34\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC34\_FORCE\_RESET}}
\DoxyCodeLine{03435\ \textcolor{preprocessor}{\#define\ \_\_ADC34\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC34\_RELEASE\_RESET}}
\DoxyCodeLine{03436\ \textcolor{preprocessor}{\#define\ \_\_DAC2\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC2\_FORCE\_RESET}}
\DoxyCodeLine{03437\ \textcolor{preprocessor}{\#define\ \_\_DAC2\_RELEASE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC2\_RELEASE\_RESET}}
\DoxyCodeLine{03438\ \textcolor{preprocessor}{\#define\ \_\_TIM18\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM18\_FORCE\_RESET}}
\DoxyCodeLine{03439\ \textcolor{preprocessor}{\#define\ \_\_TIM18\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM18\_RELEASE\_RESET}}
\DoxyCodeLine{03440\ \textcolor{preprocessor}{\#define\ \_\_TIM19\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM19\_FORCE\_RESET}}
\DoxyCodeLine{03441\ \textcolor{preprocessor}{\#define\ \_\_TIM19\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM19\_RELEASE\_RESET}}
\DoxyCodeLine{03442\ \textcolor{preprocessor}{\#define\ \_\_TIM20\_FORCE\_RESET\ \ \ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM20\_FORCE\_RESET}}
\DoxyCodeLine{03443\ \textcolor{preprocessor}{\#define\ \_\_TIM20\_RELEASE\_RESET\ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM20\_RELEASE\_RESET}}
\DoxyCodeLine{03444\ \textcolor{preprocessor}{\#define\ \_\_HRTIM1\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_HRTIM1\_FORCE\_RESET}}
\DoxyCodeLine{03445\ \textcolor{preprocessor}{\#define\ \_\_HRTIM1\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_HRTIM1\_RELEASE\_RESET}}
\DoxyCodeLine{03446\ \textcolor{preprocessor}{\#define\ \_\_SDADC1\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC1\_FORCE\_RESET}}
\DoxyCodeLine{03447\ \textcolor{preprocessor}{\#define\ \_\_SDADC2\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC2\_FORCE\_RESET}}
\DoxyCodeLine{03448\ \textcolor{preprocessor}{\#define\ \_\_SDADC3\_FORCE\_RESET\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_SDADC3\_FORCE\_RESET}}
\DoxyCodeLine{03449\ \textcolor{preprocessor}{\#define\ \_\_SDADC1\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_SDADC1\_RELEASE\_RESET}}
\DoxyCodeLine{03450\ \textcolor{preprocessor}{\#define\ \_\_SDADC2\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_SDADC2\_RELEASE\_RESET}}
\DoxyCodeLine{03451\ \textcolor{preprocessor}{\#define\ \_\_SDADC3\_RELEASE\_RESET\ \ \ \ \ \ \_\_HAL\_RCC\_SDADC3\_RELEASE\_RESET}}
\DoxyCodeLine{03452\ }
\DoxyCodeLine{03453\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_ADC1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03454\ \textcolor{preprocessor}{\#define\ \_\_ADC1\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_ADC1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03455\ \textcolor{preprocessor}{\#define\ \_\_ADC12\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_ADC12\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03456\ \textcolor{preprocessor}{\#define\ \_\_ADC12\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_ADC12\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03457\ \textcolor{preprocessor}{\#define\ \_\_ADC34\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_ADC34\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03458\ \textcolor{preprocessor}{\#define\ \_\_ADC34\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_ADC34\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03459\ \textcolor{preprocessor}{\#define\ \_\_CEC\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_CEC\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03460\ \textcolor{preprocessor}{\#define\ \_\_CEC\_IS\_CLK\_DISABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_CEC\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03461\ \textcolor{preprocessor}{\#define\ \_\_CRC\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_CRC\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03462\ \textcolor{preprocessor}{\#define\ \_\_CRC\_IS\_CLK\_DISABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_CRC\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03463\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03464\ \textcolor{preprocessor}{\#define\ \_\_DAC1\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_DAC1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03465\ \textcolor{preprocessor}{\#define\ \_\_DAC2\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_DAC2\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03466\ \textcolor{preprocessor}{\#define\ \_\_DAC2\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_DAC2\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03467\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03468\ \textcolor{preprocessor}{\#define\ \_\_DMA1\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_DMA1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03469\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_DMA2\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03470\ \textcolor{preprocessor}{\#define\ \_\_DMA2\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_DMA2\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03471\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_FLITF\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03472\ \textcolor{preprocessor}{\#define\ \_\_FLITF\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_FLITF\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03473\ \textcolor{preprocessor}{\#define\ \_\_FMC\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_FMC\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03474\ \textcolor{preprocessor}{\#define\ \_\_FMC\_IS\_CLK\_DISABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_FMC\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03475\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOA\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03476\ \textcolor{preprocessor}{\#define\ \_\_GPIOA\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOA\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03477\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOB\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03478\ \textcolor{preprocessor}{\#define\ \_\_GPIOB\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOB\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03479\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOC\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03480\ \textcolor{preprocessor}{\#define\ \_\_GPIOC\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOC\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03481\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOD\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03482\ \textcolor{preprocessor}{\#define\ \_\_GPIOD\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOD\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03483\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOE\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03484\ \textcolor{preprocessor}{\#define\ \_\_GPIOE\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOE\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03485\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOF\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03486\ \textcolor{preprocessor}{\#define\ \_\_GPIOF\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOF\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03487\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOG\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03488\ \textcolor{preprocessor}{\#define\ \_\_GPIOG\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOG\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03489\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_IS\_CLK\_ENABLED\ \ \ \ \ \ \_\_HAL\_RCC\_GPIOH\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03490\ \textcolor{preprocessor}{\#define\ \_\_GPIOH\_IS\_CLK\_DISABLED\ \ \ \ \ \_\_HAL\_RCC\_GPIOH\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03491\ \textcolor{preprocessor}{\#define\ \_\_HRTIM1\_IS\_CLK\_ENABLED\ \ \ \ \ \_\_HAL\_RCC\_HRTIM1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03492\ \textcolor{preprocessor}{\#define\ \_\_HRTIM1\_IS\_CLK\_DISABLED\ \ \ \ \_\_HAL\_RCC\_HRTIM1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03493\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_I2C1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03494\ \textcolor{preprocessor}{\#define\ \_\_I2C1\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_I2C1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03495\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_I2C2\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03496\ \textcolor{preprocessor}{\#define\ \_\_I2C2\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_I2C2\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03497\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_I2C3\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03498\ \textcolor{preprocessor}{\#define\ \_\_I2C3\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_I2C3\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03499\ \textcolor{preprocessor}{\#define\ \_\_PWR\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \ \_\_HAL\_RCC\_PWR\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03500\ \textcolor{preprocessor}{\#define\ \_\_PWR\_IS\_CLK\_DISABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_PWR\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03501\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_IS\_CLK\_ENABLED\ \ \ \ \ \_\_HAL\_RCC\_SYSCFG\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03502\ \textcolor{preprocessor}{\#define\ \_\_SYSCFG\_IS\_CLK\_DISABLED\ \ \ \ \_\_HAL\_RCC\_SYSCFG\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03503\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03504\ \textcolor{preprocessor}{\#define\ \_\_SPI1\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_SPI1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03505\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI2\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03506\ \textcolor{preprocessor}{\#define\ \_\_SPI2\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_SPI2\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03507\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI3\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03508\ \textcolor{preprocessor}{\#define\ \_\_SPI3\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_SPI3\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03509\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_SPI4\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03510\ \textcolor{preprocessor}{\#define\ \_\_SPI4\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_SPI4\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03511\ \textcolor{preprocessor}{\#define\ \_\_SDADC1\_IS\_CLK\_ENABLED\ \ \ \ \ \_\_HAL\_RCC\_SDADC1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03512\ \textcolor{preprocessor}{\#define\ \_\_SDADC1\_IS\_CLK\_DISABLED\ \ \ \ \_\_HAL\_RCC\_SDADC1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03513\ \textcolor{preprocessor}{\#define\ \_\_SDADC2\_IS\_CLK\_ENABLED\ \ \ \ \ \_\_HAL\_RCC\_SDADC2\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03514\ \textcolor{preprocessor}{\#define\ \_\_SDADC2\_IS\_CLK\_DISABLED\ \ \ \ \_\_HAL\_RCC\_SDADC2\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03515\ \textcolor{preprocessor}{\#define\ \_\_SDADC3\_IS\_CLK\_ENABLED\ \ \ \ \ \_\_HAL\_RCC\_SDADC3\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03516\ \textcolor{preprocessor}{\#define\ \_\_SDADC3\_IS\_CLK\_DISABLED\ \ \ \ \_\_HAL\_RCC\_SDADC3\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03517\ \textcolor{preprocessor}{\#define\ \_\_SRAM\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_SRAM\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03518\ \textcolor{preprocessor}{\#define\ \_\_SRAM\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_SRAM\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03519\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM1\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03520\ \textcolor{preprocessor}{\#define\ \_\_TIM1\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_TIM1\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03521\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM2\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03522\ \textcolor{preprocessor}{\#define\ \_\_TIM2\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_TIM2\_IS\_CLK\_DISABLED}}
\DoxyCodeLine{03523\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_IS\_CLK\_ENABLED\ \ \ \ \ \ \ \_\_HAL\_RCC\_TIM3\_IS\_CLK\_ENABLED}}
\DoxyCodeLine{03524\ \textcolor{preprocessor}{\#define\ \_\_TIM3\_IS\_CLK\_DISABLED\ \ \ \ \ \ \_\_HAL\_RCC\_TIM3\_IS\_CLK\_DISABLED}}
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\DoxyCodeLine{04222\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_DISABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_DISABLE\_IT}}
\DoxyCodeLine{04223\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_GET\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_GET\_FLAG}}
\DoxyCodeLine{04224\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_CLEAR\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_CLEAR\_FLAG}}
\DoxyCodeLine{04225\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_SET\_RISING\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_ENABLE\_RISING\_EDGE}}
\DoxyCodeLine{04226\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_SET\_FALLING\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_ENABLE\_FALLING\_EDGE}}
\DoxyCodeLine{04227\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_SET\_FALLINGRISING\_TRIGGER\ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}}
\DoxyCodeLine{04228\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_FS\_EXTI\_GENERATE\_SWIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_FS\_WAKEUP\_EXTI\_GENERATE\_SWIT}}
\DoxyCodeLine{04229\ }
\DoxyCodeLine{04230\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_ENABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_ENABLE\_IT}}
\DoxyCodeLine{04231\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_DISABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_DISABLE\_IT}}
\DoxyCodeLine{04232\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_GET\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_GET\_FLAG}}
\DoxyCodeLine{04233\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_CLEAR\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_CLEAR\_FLAG}}
\DoxyCodeLine{04234\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_SET\_RISING\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_ENABLE\_RISING\_EDGE}}
\DoxyCodeLine{04235\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_SET\_FALLING\_EGDE\_TRIGGER\ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_ENABLE\_FALLING\_EDGE}}
\DoxyCodeLine{04236\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_SET\_FALLINGRISING\_TRIGGER\ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_ENABLE\_RISING\_FALLING\_EDGE}}
\DoxyCodeLine{04237\ \textcolor{preprocessor}{\#define\ \_\_HAL\_USB\_HS\_EXTI\_GENERATE\_SWIT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_USB\_OTG\_HS\_WAKEUP\_EXTI\_GENERATE\_SWIT}}
\DoxyCodeLine{04238\ }
\DoxyCodeLine{04239\ \textcolor{preprocessor}{\#define\ HAL\_PCD\_ActiveRemoteWakeup\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PCD\_ActivateRemoteWakeup}}
\DoxyCodeLine{04240\ \textcolor{preprocessor}{\#define\ HAL\_PCD\_DeActiveRemoteWakeup\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PCD\_DeActivateRemoteWakeup}}
\DoxyCodeLine{04241\ }
\DoxyCodeLine{04242\ \textcolor{preprocessor}{\#define\ HAL\_PCD\_SetTxFiFo\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PCDEx\_SetTxFiFo}}
\DoxyCodeLine{04243\ \textcolor{preprocessor}{\#define\ HAL\_PCD\_SetRxFiFo\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ HAL\_PCDEx\_SetRxFiFo}}
\DoxyCodeLine{04244\ \textcolor{preprocessor}{\#if\ defined(STM32U5)}}
\DoxyCodeLine{04245\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GOTGCTL\_BSESVLD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GOTGCTL\_BSVLD}}
\DoxyCodeLine{04246\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GAHBCFG\_GINT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GAHBCFG\_GINTMSK}}
\DoxyCodeLine{04247\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GUSBCFG\_PHYLPCS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GUSBCFG\_PHYLPC}}
\DoxyCodeLine{04248\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GRSTCTL\_HSRST\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GRSTCTL\_PSRST}}
\DoxyCodeLine{04249\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GINTSTS\_BOUTNAKEFF\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GINTSTS\_GONAKEFF}}
\DoxyCodeLine{04250\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GINTSTS\_WKUINT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GINTSTS\_WKUPINT}}
\DoxyCodeLine{04251\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GINTMSK\_PXFRM\_IISOOXFRM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GINTMSK\_IPXFRM\_IISOOXFRM}}
\DoxyCodeLine{04252\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GRXSTSP\_EPNUM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GRXSTSP\_EPNUM\_CHNUM}}
\DoxyCodeLine{04253\ \textcolor{preprocessor}{\#define\ USB\_OTG\_GLPMCFG\_L1ResumeOK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_GLPMCFG\_L1RSMOK}}
\DoxyCodeLine{04254\ \textcolor{preprocessor}{\#define\ USB\_OTG\_HPTXFSIZ\_PTXFD\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_HPTXFSIZ\_PTXFSIZ}}
\DoxyCodeLine{04255\ \textcolor{preprocessor}{\#define\ USB\_OTG\_HCCHAR\_MC\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_HCCHAR\_MCNT}}
\DoxyCodeLine{04256\ \textcolor{preprocessor}{\#define\ USB\_OTG\_HCCHAR\_MC\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_HCCHAR\_MCNT\_0}}
\DoxyCodeLine{04257\ \textcolor{preprocessor}{\#define\ USB\_OTG\_HCCHAR\_MC\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_HCCHAR\_MCNT\_1}}
\DoxyCodeLine{04258\ \textcolor{preprocessor}{\#define\ USB\_OTG\_HCINTMSK\_AHBERR\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_HCINTMSK\_AHBERRM}}
\DoxyCodeLine{04259\ \textcolor{preprocessor}{\#define\ USB\_OTG\_HCTSIZ\_DOPING\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_HCTSIZ\_DOPNG}}
\DoxyCodeLine{04260\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DOEPMSK\_OPEM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DOEPMSK\_OUTPKTERRM}}
\DoxyCodeLine{04261\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DIEPCTL\_SODDFRM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DIEPCTL\_SD1PID\_SODDFRM}}
\DoxyCodeLine{04262\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DIEPTSIZ\_MULCNT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DIEPTSIZ\_MCNT}}
\DoxyCodeLine{04263\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DOEPCTL\_SODDFRM\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DOEPCTL\_SD1PID\_SODDFRM}}
\DoxyCodeLine{04264\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DOEPCTL\_DPID\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DOEPCTL\_DPID\_EONUM}}
\DoxyCodeLine{04265\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DOEPTSIZ\_STUPCNT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DOEPTSIZ\_RXDPID}}
\DoxyCodeLine{04266\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DOEPTSIZ\_STUPCNT\_0\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DOEPTSIZ\_RXDPID\_0}}
\DoxyCodeLine{04267\ \textcolor{preprocessor}{\#define\ USB\_OTG\_DOEPTSIZ\_STUPCNT\_1\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_DOEPTSIZ\_RXDPID\_1}}
\DoxyCodeLine{04268\ \textcolor{preprocessor}{\#define\ USB\_OTG\_PCGCCTL\_STOPCLK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_PCGCCTL\_STPPCLK}}
\DoxyCodeLine{04269\ \textcolor{preprocessor}{\#define\ USB\_OTG\_PCGCCTL\_GATECLK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ USB\_OTG\_PCGCCTL\_GATEHCLK}}
\DoxyCodeLine{04270\ \textcolor{preprocessor}{\#endif}\textcolor{preprocessor}{}}
\DoxyCodeLine{04274\ }
\DoxyCodeLine{04278\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_SetICPrescalerValue\ \ \ TIM\_SET\_ICPRESCALERVALUE}}
\DoxyCodeLine{04279\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_ResetICPrescalerValue\ TIM\_RESET\_ICPRESCALERVALUE}}
\DoxyCodeLine{04280\ }
\DoxyCodeLine{04281\ \textcolor{preprocessor}{\#define\ TIM\_GET\_ITSTATUS\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_GET\_IT\_SOURCE}}
\DoxyCodeLine{04282\ \textcolor{preprocessor}{\#define\ TIM\_GET\_CLEAR\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_CLEAR\_IT}}
\DoxyCodeLine{04283\ }
\DoxyCodeLine{04284\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_GET\_ITSTATUS\ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_GET\_IT\_SOURCE}}
\DoxyCodeLine{04285\ }
\DoxyCodeLine{04286\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_DIRECTION\_STATUS\ \ \ \ \ \ \_\_HAL\_TIM\_IS\_TIM\_COUNTING\_DOWN}}
\DoxyCodeLine{04287\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_PRESCALER\ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_SET\_PRESCALER}}
\DoxyCodeLine{04288\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_SetCounter\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_SET\_COUNTER}}
\DoxyCodeLine{04289\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_GetCounter\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_GET\_COUNTER}}
\DoxyCodeLine{04290\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_SetAutoreload\ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_SET\_AUTORELOAD}}
\DoxyCodeLine{04291\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_GetAutoreload\ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_GET\_AUTORELOAD}}
\DoxyCodeLine{04292\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_SetClockDivision\ \ \ \ \ \ \_\_HAL\_TIM\_SET\_CLOCKDIVISION}}
\DoxyCodeLine{04293\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_GetClockDivision\ \ \ \ \ \ \_\_HAL\_TIM\_GET\_CLOCKDIVISION}}
\DoxyCodeLine{04294\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_SetICPrescaler\ \ \ \ \ \ \ \ \_\_HAL\_TIM\_SET\_ICPRESCALER}}
\DoxyCodeLine{04295\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_GetICPrescaler\ \ \ \ \ \ \ \ \_\_HAL\_TIM\_GET\_ICPRESCALER}}
\DoxyCodeLine{04296\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_SetCompare\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_SET\_COMPARE}}
\DoxyCodeLine{04297\ \textcolor{preprocessor}{\#define\ \_\_HAL\_TIM\_GetCompare\ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_TIM\_GET\_COMPARE}}
\DoxyCodeLine{04298\ }
\DoxyCodeLine{04299\ \textcolor{preprocessor}{\#define\ TIM\_BREAKINPUTSOURCE\_DFSDM\ \ TIM\_BREAKINPUTSOURCE\_DFSDM1}}
\DoxyCodeLine{04300\ }
\DoxyCodeLine{04301\ \textcolor{preprocessor}{\#define\ TIM\_OCMODE\_ASSYMETRIC\_PWM1\ \ \ \ \ \ TIM\_OCMODE\_ASYMMETRIC\_PWM1}}
\DoxyCodeLine{04302\ \textcolor{preprocessor}{\#define\ TIM\_OCMODE\_ASSYMETRIC\_PWM2\ \ \ \ \ \ TIM\_OCMODE\_ASYMMETRIC\_PWM2}\textcolor{preprocessor}{}}
\DoxyCodeLine{04306\ }
\DoxyCodeLine{04310\ }
\DoxyCodeLine{04311\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_ENABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_ENABLE\_IT}}
\DoxyCodeLine{04312\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_DISABLE\_IT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_DISABLE\_IT}}
\DoxyCodeLine{04313\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_GET\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_GET\_FLAG}}
\DoxyCodeLine{04314\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_CLEAR\_FLAG\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_CLEAR\_FLAG}}
\DoxyCodeLine{04315\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_SET\_RISING\_EGDE\_TRIGGER\ \ \ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_ENABLE\_RISING\_EDGE\_TRIGGER}}
\DoxyCodeLine{04316\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_SET\_FALLING\_EGDE\_TRIGGER\ \ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_ENABLE\_FALLING\_EDGE\_TRIGGER}}
\DoxyCodeLine{04317\ \textcolor{preprocessor}{\#define\ \_\_HAL\_ETH\_EXTI\_SET\_FALLINGRISING\_TRIGGER\ \ \ \_\_HAL\_ETH\_WAKEUP\_EXTI\_ENABLE\_FALLINGRISING\_TRIGGER}}
\DoxyCodeLine{04318\ }
\DoxyCodeLine{04319\ \textcolor{preprocessor}{\#define\ ETH\_PROMISCIOUSMODE\_ENABLE\ \ \ ETH\_PROMISCUOUS\_MODE\_ENABLE}}
\DoxyCodeLine{04320\ \textcolor{preprocessor}{\#define\ ETH\_PROMISCIOUSMODE\_DISABLE\ \ ETH\_PROMISCUOUS\_MODE\_DISABLE}}
\DoxyCodeLine{04321\ \textcolor{preprocessor}{\#define\ IS\_ETH\_PROMISCIOUS\_MODE\ \ \ \ \ \ IS\_ETH\_PROMISCUOUS\_MODE}\textcolor{preprocessor}{}}
\DoxyCodeLine{04325\ }
\DoxyCodeLine{04329\ \textcolor{preprocessor}{\#define\ \_\_HAL\_LTDC\_LAYER\ LTDC\_LAYER}}
\DoxyCodeLine{04330\ \textcolor{preprocessor}{\#define\ \_\_HAL\_LTDC\_RELOAD\_CONFIG\ \ \_\_HAL\_LTDC\_RELOAD\_IMMEDIATE\_CONFIG}\textcolor{preprocessor}{}}
\DoxyCodeLine{04334\ }
\DoxyCodeLine{04338\ \textcolor{preprocessor}{\#define\ SAI\_OUTPUTDRIVE\_DISABLED\ \ \ \ \ \ \ \ \ \ SAI\_OUTPUTDRIVE\_DISABLE}}
\DoxyCodeLine{04339\ \textcolor{preprocessor}{\#define\ SAI\_OUTPUTDRIVE\_ENABLED\ \ \ \ \ \ \ \ \ \ \ SAI\_OUTPUTDRIVE\_ENABLE}}
\DoxyCodeLine{04340\ \textcolor{preprocessor}{\#define\ SAI\_MASTERDIVIDER\_ENABLED\ \ \ \ \ \ \ \ \ SAI\_MASTERDIVIDER\_ENABLE}}
\DoxyCodeLine{04341\ \textcolor{preprocessor}{\#define\ SAI\_MASTERDIVIDER\_DISABLED\ \ \ \ \ \ \ \ SAI\_MASTERDIVIDER\_DISABLE}}
\DoxyCodeLine{04342\ \textcolor{preprocessor}{\#define\ SAI\_STREOMODE\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SAI\_STEREOMODE}}
\DoxyCodeLine{04343\ \textcolor{preprocessor}{\#define\ SAI\_FIFOStatus\_Empty\ \ \ \ \ \ \ \ \ \ \ \ \ \ SAI\_FIFOSTATUS\_EMPTY}}
\DoxyCodeLine{04344\ \textcolor{preprocessor}{\#define\ SAI\_FIFOStatus\_Less1QuarterFull\ \ \ SAI\_FIFOSTATUS\_LESS1QUARTERFULL}}
\DoxyCodeLine{04345\ \textcolor{preprocessor}{\#define\ SAI\_FIFOStatus\_1QuarterFull\ \ \ \ \ \ \ SAI\_FIFOSTATUS\_1QUARTERFULL}}
\DoxyCodeLine{04346\ \textcolor{preprocessor}{\#define\ SAI\_FIFOStatus\_HalfFull\ \ \ \ \ \ \ \ \ \ \ SAI\_FIFOSTATUS\_HALFFULL}}
\DoxyCodeLine{04347\ \textcolor{preprocessor}{\#define\ SAI\_FIFOStatus\_3QuartersFull\ \ \ \ \ \ SAI\_FIFOSTATUS\_3QUARTERFULL}}
\DoxyCodeLine{04348\ \textcolor{preprocessor}{\#define\ SAI\_FIFOStatus\_Full\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SAI\_FIFOSTATUS\_FULL}}
\DoxyCodeLine{04349\ \textcolor{preprocessor}{\#define\ IS\_SAI\_BLOCK\_MONO\_STREO\_MODE\ \ \ \ \ \ IS\_SAI\_BLOCK\_MONO\_STEREO\_MODE}}
\DoxyCodeLine{04350\ \textcolor{preprocessor}{\#define\ SAI\_SYNCHRONOUS\_EXT\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ SAI\_SYNCHRONOUS\_EXT\_SAI1}}
\DoxyCodeLine{04351\ \textcolor{preprocessor}{\#define\ SAI\_SYNCEXT\_IN\_ENABLE\ \ \ \ \ \ \ \ \ \ \ \ \ SAI\_SYNCEXT\_OUTBLOCKA\_ENABLE}\textcolor{preprocessor}{}}
\DoxyCodeLine{04355\ }
\DoxyCodeLine{04359\ \textcolor{preprocessor}{\#if\ defined(STM32H7)}}
\DoxyCodeLine{04360\ \textcolor{preprocessor}{\#define\ HAL\_SPDIFRX\_ReceiveControlFlow\ \ \ \ \ \ HAL\_SPDIFRX\_ReceiveCtrlFlow}}
\DoxyCodeLine{04361\ \textcolor{preprocessor}{\#define\ HAL\_SPDIFRX\_ReceiveControlFlow\_IT\ \ \ HAL\_SPDIFRX\_ReceiveCtrlFlow\_IT}}
\DoxyCodeLine{04362\ \textcolor{preprocessor}{\#define\ HAL\_SPDIFRX\_ReceiveControlFlow\_DMA\ \ HAL\_SPDIFRX\_ReceiveCtrlFlow\_DMA}}
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\DoxyCodeLine{04367\ }
\DoxyCodeLine{04371\ \textcolor{preprocessor}{\#if\ defined\ (STM32H7)\ ||\ defined\ (STM32G4)\ ||\ defined\ (STM32F3)}}
\DoxyCodeLine{04372\ \textcolor{preprocessor}{\#define\ HAL\_HRTIM\_WaveformCounterStart\_IT\ \ \ \ \ \ HAL\_HRTIM\_WaveformCountStart\_IT}}
\DoxyCodeLine{04373\ \textcolor{preprocessor}{\#define\ HAL\_HRTIM\_WaveformCounterStart\_DMA\ \ \ \ \ HAL\_HRTIM\_WaveformCountStart\_DMA}}
\DoxyCodeLine{04374\ \textcolor{preprocessor}{\#define\ HAL\_HRTIM\_WaveformCounterStart\ \ \ \ \ \ \ \ \ HAL\_HRTIM\_WaveformCountStart}}
\DoxyCodeLine{04375\ \textcolor{preprocessor}{\#define\ HAL\_HRTIM\_WaveformCounterStop\_IT\ \ \ \ \ \ \ HAL\_HRTIM\_WaveformCountStop\_IT}}
\DoxyCodeLine{04376\ \textcolor{preprocessor}{\#define\ HAL\_HRTIM\_WaveformCounterStop\_DMA\ \ \ \ \ \ HAL\_HRTIM\_WaveformCountStop\_DMA}}
\DoxyCodeLine{04377\ \textcolor{preprocessor}{\#define\ HAL\_HRTIM\_WaveformCounterStop\ \ \ \ \ \ \ \ \ \ HAL\_HRTIM\_WaveformCountStop}}
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\DoxyCodeLine{04382\ }
\DoxyCodeLine{04386\ \textcolor{preprocessor}{\#if\ defined\ (STM32L4)\ ||\ defined\ (STM32F4)\ ||\ defined\ (STM32F7)\ ||\ defined(STM32H7)}}
\DoxyCodeLine{04387\ \textcolor{preprocessor}{\#define\ HAL\_QPSI\_TIMEOUT\_DEFAULT\_VALUE\ HAL\_QSPI\_TIMEOUT\_DEFAULT\_VALUE}}
\DoxyCodeLine{04388\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32L4\ ||\ STM32F4\ ||\ STM32F7\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{04392\ }
\DoxyCodeLine{04396\ \textcolor{preprocessor}{\#if\ defined\ (STM32F7)}}
\DoxyCodeLine{04397\ \textcolor{preprocessor}{\#define\ ART\_ACCLERATOR\_ENABLE\ ART\_ACCELERATOR\_ENABLE}}
\DoxyCodeLine{04398\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32F7\ */}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{04402\ }
\DoxyCodeLine{04406\ }
\DoxyCodeLine{04410\ }
\DoxyCodeLine{04411\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{04412\ \}}
\DoxyCodeLine{04413\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{04414\ }
\DoxyCodeLine{04415\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32\_HAL\_LEGACY\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{04416\ }
\DoxyCodeLine{04417\ }

\end{DoxyCode}
